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Added DESIGN to RTL simulation docs for clarity

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Dinesh Parimi 2019-01-13 03:20:47 -08:00 committed by GitHub
parent 844ff9f761
commit 7c4cc552e6
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1 changed files with 2 additions and 2 deletions
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docs/Advanced-Usage/Debugging/RTL-Simulation.rst
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@ -109,7 +109,7 @@ Run rv64ui-p-simple (a single assembly test) on a verilated simulator.
::
make DESIGN=FireSimNoNIC
make $(pwd)/output/f1/FireSimNoNIC-FireSimRocketChipConfig-FireSimConfig/rv64ui-p-simple.out
make DESIGN=FireSimNoNIC $(pwd)/output/f1/FireSimNoNIC-FireSimRocketChipConfig-FireSimConfig/rv64ui-p-simple.out
Run rv64ui-p-simple (a single assembly test) on a VCS simulator with waveform dumping.
@ -117,7 +117,7 @@ Run rv64ui-p-simple (a single assembly test) on a VCS simulator with waveform du
make DESIGN=FireSimNoNIC vcs-debug
make EMUL=vcs $(pwd)/output/f1/FireSimNoNIC-FireSimRocketChipConfig-FireSimConfig/rv64ui-p-simple.vpd
make DESIGN=FireSimNoNIC EMUL=vcs $(pwd)/output/f1/FireSimNoNIC-FireSimRocketChipConfig-FireSimConfig/rv64ui-p-simple.vpd
FPGA-Level Simulation