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Merge pull request #113 from firesim/bump-rc-july-3-2018-v2 

Bump Rocket Chip to July 3 2018
This commit is contained in:
Sagar Karandikar 2018-09-23 12:27:43 -07:00 committed by GitHub
parent 58e5d6934a 7628ca0214
commit 778a6b76b5
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
16 changed files with 84 additions and 108 deletions
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20
deploy/sample-backup-configs/sample_config_build.ini
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@ -12,26 +12,26 @@ spotmaxprice=ondemand
# this section references builds defined in config_build_recipes.ini
# if you add a build here, it will be built when you run buildafi
firesim-singlecore-no-nic-lbp
firesim-singlecore-nic-lbp
firesim-quadcore-no-nic-lbp
firesim-quadcore-nic-lbp
#firesim-singlecore-nic-lbp
#firesim-quadcore-no-nic-lbp
#firesim-quadcore-nic-lbp
firesim-quadcore-no-nic-ddr3-llc4mb
firesim-quadcore-nic-ddr3-llc4mb
fireboom-singlecore-no-nic-lbp
#fireboom-singlecore-no-nic-lbp
fireboom-singlecore-no-nic-ddr3-llc4mb
fireboom-singlecore-nic-lbp
#fireboom-singlecore-nic-lbp
fireboom-singlecore-nic-ddr3-llc4mb
[agfistoshare]
firesim-singlecore-no-nic-lbp
firesim-singlecore-nic-lbp
firesim-quadcore-no-nic-lbp
firesim-quadcore-nic-lbp
#firesim-singlecore-nic-lbp
#firesim-quadcore-no-nic-lbp
#firesim-quadcore-nic-lbp
firesim-quadcore-no-nic-ddr3-llc4mb
firesim-quadcore-nic-ddr3-llc4mb
fireboom-singlecore-no-nic-lbp
#fireboom-singlecore-no-nic-lbp
fireboom-singlecore-no-nic-ddr3-llc4mb
fireboom-singlecore-nic-lbp
#fireboom-singlecore-nic-lbp
fireboom-singlecore-nic-ddr3-llc4mb
[sharewithaccounts]

62
deploy/sample-backup-configs/sample_config_build_recipes.ini
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@ -5,12 +5,12 @@
# edit config_build.ini to actually "turn on" a config to be built when you run
# buildafi
[firesim-singlecore-nic-lbp]
DESIGN=FireSim
TARGET_CONFIG=FireSimRocketChipSingleCoreConfig
PLATFORM_CONFIG=FireSimConfig
instancetype=c4.4xlarge
deploytriplet=None
#[firesim-singlecore-nic-lbp]
#DESIGN=FireSim
#TARGET_CONFIG=FireSimRocketChipSingleCoreConfig
#PLATFORM_CONFIG=FireSimConfig
#instancetype=c4.4xlarge
#deploytriplet=None
[firesim-singlecore-no-nic-lbp]
DESIGN=FireSimNoNIC
@ -19,19 +19,19 @@ PLATFORM_CONFIG=FireSimConfig
instancetype=c4.4xlarge
deploytriplet=None
[firesim-quadcore-nic-lbp]
DESIGN=FireSim
TARGET_CONFIG=FireSimRocketChipQuadCoreConfig
PLATFORM_CONFIG=FireSimConfig
instancetype=c4.4xlarge
deploytriplet=None
[firesim-quadcore-no-nic-lbp]
DESIGN=FireSimNoNIC
TARGET_CONFIG=FireSimRocketChipQuadCoreConfig
PLATFORM_CONFIG=FireSimConfig
instancetype=c4.4xlarge
deploytriplet=None
#[firesim-quadcore-nic-lbp]
#DESIGN=FireSim
#TARGET_CONFIG=FireSimRocketChipQuadCoreConfig
#PLATFORM_CONFIG=FireSimConfig
#instancetype=c4.4xlarge
#deploytriplet=None
#
#[firesim-quadcore-no-nic-lbp]
#DESIGN=FireSimNoNIC
#TARGET_CONFIG=FireSimRocketChipQuadCoreConfig
#PLATFORM_CONFIG=FireSimConfig
#instancetype=c4.4xlarge
#deploytriplet=None
[firesim-quadcore-nic-ddr3-llc4mb]
DESIGN=FireSim
@ -48,12 +48,12 @@ instancetype=c4.4xlarge
deploytriplet=None
# BOOM-based targets
[fireboom-singlecore-no-nic-lbp]
DESIGN=FireBoomNoNIC
TARGET_CONFIG=FireSimBoomConfig
PLATFORM_CONFIG=FireSimConfig
instancetype=c4.4xlarge
deploytriplet=None
#[fireboom-singlecore-no-nic-lbp]
#DESIGN=FireBoomNoNIC
#TARGET_CONFIG=FireSimBoomConfig
#PLATFORM_CONFIG=FireSimConfig
#instancetype=c4.4xlarge
#deploytriplet=None
[fireboom-singlecore-no-nic-ddr3-llc4mb]
DESIGN=FireBoomNoNIC
@ -62,12 +62,12 @@ PLATFORM_CONFIG=FireSimDDR3FRFCFSLLC4MBConfig
instancetype=c4.4xlarge
deploytriplet=None
[fireboom-singlecore-nic-lbp]
DESIGN=FireBoom
TARGET_CONFIG=FireSimBoomConfig
PLATFORM_CONFIG=FireSimConfig
instancetype=c4.4xlarge
deploytriplet=None
#[fireboom-singlecore-nic-lbp]
#DESIGN=FireBoom
#TARGET_CONFIG=FireSimBoomConfig
#PLATFORM_CONFIG=FireSimConfig
#instancetype=c4.4xlarge
#deploytriplet=None
[fireboom-singlecore-nic-ddr3-llc4mb]
DESIGN=FireBoom

43
deploy/sample-backup-configs/sample_config_hwdb.ini
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@ -9,52 +9,19 @@
# If you are using an older version of FireSim, you will need to generate your
# own images.
[fireboom-singlecore-nic-ddr3-llc4mb]
agfi=agfi-06a2d40b49e1a1034
deploytripletoverride=None
customruntimeconfig=None
[fireboom-singlecore-nic-lbp]
agfi=agfi-06f0280bc843bc13e
deploytripletoverride=None
customruntimeconfig=None
[fireboom-singlecore-no-nic-ddr3-llc4mb]
agfi=agfi-06af32e23be49f5d0
deploytripletoverride=None
customruntimeconfig=None
[fireboom-singlecore-no-nic-lbp]
agfi=agfi-0673639cb9ae9d4d0
deploytripletoverride=None
customruntimeconfig=None
[firesim-quadcore-nic-ddr3-llc4mb]
agfi=agfi-01fcd09aa9a22a81e
deploytripletoverride=None
customruntimeconfig=None
[firesim-quadcore-nic-lbp]
agfi=agfi-034d73970b3ff9b33
agfi=agfi-0363594a482851ec5
deploytripletoverride=None
customruntimeconfig=None
[firesim-quadcore-no-nic-ddr3-llc4mb]
agfi=agfi-07a1d8925c3b9213f
deploytripletoverride=None
customruntimeconfig=None
[firesim-quadcore-no-nic-lbp]
agfi=agfi-03ba523656104145a
deploytripletoverride=None
customruntimeconfig=None
[firesim-singlecore-nic-lbp]
agfi=agfi-00df7bcf8f8374b5b
agfi=agfi-04c48101af4a6e84a
deploytripletoverride=None
customruntimeconfig=None
[firesim-singlecore-no-nic-lbp]
agfi=agfi-061edbd6ddf2b1dee
agfi=agfi-08e0a4ad02494f1ac
deploytripletoverride=None
customruntimeconfig=None
### TODO: BOOM configs will be readded once support is added back to FireChip

4
sim/Makefile
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@ -18,9 +18,9 @@ TARGET_PROJECT_MAKEFRAG ?= src/main/makefrag/$(TARGET_PROJECT)/Makefrag
default: compile
SBT ?= sbt
SBT_FLAGS ?= -J-Xmx16G -J-Xss8M -J-XX:MaxPermSize=256M -J-XX:MaxMetaspaceSize=512M -J-XX:ReservedCodeCacheSize=1G
SBT_FLAGS ?= -J-Xmx16G -J-Xss8M -J-XX:MaxPermSize=256M -J-XX:MaxMetaspaceSize=512M -J-XX:ReservedCodeCacheSize=1G ++2.12.4
sbt:
$(SBT) $(SBT_FLAGS)
$(SBT) $(SBT_FLAGS) shell
test:
$(SBT) $(SBT_FLAGS) test

2
sim/barstools

@ -1 +1 @@
Subproject commit 76486586db9fa20f9aefd1aeec18d45c0015ebe1
Subproject commit 6d895c8f0e0bccbcd931384552ece3955b6bc6f8

8
sim/build.sbt
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@ -1,9 +1,9 @@
lazy val commonSettings = Seq(
organization := "berkeley",
version := "1.0",
scalaVersion := "2.11.12",
scalaVersion := "2.12.4",
traceLevel := 15,
scalacOptions ++= Seq("-deprecation","-unchecked"),
scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"),
libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.1" % "test",
libraryDependencies += "org.json4s" %% "json4s-native" % "3.5.3",
libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value,
@ -15,7 +15,7 @@ lazy val commonSettings = Seq(
)
lazy val rocketchip = RootProject(file("target-rtl/firechip/rocket-chip"))
lazy val boom = project in file("target-rtl/firechip/boom") settings commonSettings dependsOn rocketchip
//lazy val boom = project in file("target-rtl/firechip/boom") settings commonSettings dependsOn rocketchip
lazy val sifiveip = project in file("target-rtl/firechip/sifive-blocks") settings commonSettings dependsOn rocketchip
lazy val testchipip = project in file("target-rtl/firechip/testchipip") settings commonSettings dependsOn rocketchip
lazy val icenet = project in file("target-rtl/firechip/icenet") settings commonSettings dependsOn (rocketchip, testchipip)
@ -24,4 +24,4 @@ lazy val mdf = RootProject(file("barstools/mdf/scalalib"))
lazy val barstools = project in file("barstools/macros") settings commonSettings dependsOn (mdf, rocketchip)
lazy val midas = project in file("midas") settings commonSettings dependsOn barstools
lazy val firesim = project in file(".") settings commonSettings dependsOn (midas, sifiveip, testchipip, icenet, boom)
lazy val firesim = project in file(".") settings commonSettings dependsOn (midas, sifiveip, testchipip, icenet/*, boom*/)

2
sim/firrtl

@ -1 +1 @@
Subproject commit 49e7da1e2af0d5d634a8b7dafe3175348df82f13
Subproject commit b7ea6329716bb978a1953fd65a391cb76e045e0d

2
sim/midas

@ -1 +1 @@
Subproject commit c0af260b6d3a540a47f6d46e9c1cc7cc55e61153
Subproject commit 3ef827ec358f4431f3764c4022086fc19b70ea08

3
sim/src/main/cc/firesim/firesim_top.cc
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@ -206,6 +206,9 @@ void firesim_top_t::run() {
uint64_t end_time = timestamp();
double sim_time = diff_secs(end_time, start_time);
double sim_speed = ((double) cycles()) / (sim_time * 1000.0);
// always print a newline after target's output
fprintf(stderr, "\n");
if (sim_speed > 1000.0) {
fprintf(stderr, "time elapsed: %.1f s, simulation speed = %.2f MHz\n", sim_time, sim_speed / 1000.0);
} else {

2
sim/src/main/scala/endpoints/UARTWidget.scala
View File

@ -19,7 +19,7 @@ class SimUART extends Endpoint {
}
def widget(p: Parameters) = {
val frequency = p(PeripheryBusKey).frequency
val baudrate = p(PeripheryUARTKey).head.initBaudRate
val baudrate = 3686400L
val div = (p(PeripheryBusKey).frequency / baudrate).toInt
new UARTWidget(div)(p)
}

18
sim/src/main/scala/firesim/Generator.scala
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@ -14,7 +14,7 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.subsystem.RocketTilesKey
import freechips.rocketchip.tile.XLen
import boom.system.{BoomTilesKey, BoomTestSuites}
/*import boom.system.{BoomTilesKey, BoomTestSuites}*/
case class FireSimGeneratorArgs(
midasFlowKind: String = "midas", // "midas", "strober", "replay"
@ -61,9 +61,9 @@ trait HasFireSimGeneratorUtilities extends HasGeneratorUtilities with HasTestSui
implicit val valName = ValName(targetNames.topModuleClass)
targetNames.topModuleClass match {
case "FireSim" => LazyModule(new FireSim()(params)).module
case "FireBoom" => LazyModule(new FireBoom()(params)).module
// case "FireBoom" => LazyModule(new FireBoom()(params)).module
case "FireSimNoNIC" => LazyModule(new FireSimNoNIC()(params)).module
case "FireBoomNoNIC" => LazyModule(new FireBoomNoNIC()(params)).module
// case "FireBoomNoNIC" => LazyModule(new FireBoomNoNIC()(params)).module
}
}
@ -163,11 +163,11 @@ trait HasTestSuites {
def addTestSuites(params: Parameters) {
val coreParams =
if (params(RocketTilesKey).nonEmpty) {
// if (params(RocketTilesKey).nonEmpty) {
params(RocketTilesKey).head.core
} else {
params(BoomTilesKey).head.core
}
// } else {
// params(BoomTilesKey).head.core
// }
val xlen = params(XLen)
val vm = coreParams.useVM
val env = if (vm) List("p","v") else List("p")
@ -186,8 +186,8 @@ trait HasTestSuites {
if (coreParams.useAtomics) TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
val (rvi, rvu) =
if (params(BoomTilesKey).nonEmpty) ((if (vm) BoomTestSuites.rv64i else BoomTestSuites.rv64pi), rv64u)
else if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
/* if (params(BoomTilesKey).nonEmpty) ((if (vm) BoomTestSuites.rv64i else BoomTestSuites.rv64pi), rv64u)
else */if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
else ((if (vm) rv32i else rv32pi), rv32u)
TestGeneration.addSuites(rvi.map(_("p")))

13
sim/src/main/scala/firesim/TargetConfigs.scala
View File

@ -5,7 +5,7 @@ import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink.BootROMParams
import boom.system.BoomTilesKey
/*import boom.system.BoomTilesKey*/
import testchipip.{WithBlockDevice, BlockDeviceKey, BlockDeviceConfig}
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import icenet._
@ -22,7 +22,8 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) =>
class WithUARTKey extends Config((site, here, up) => {
case PeripheryUARTKey => List(UARTParams(
address = BigInt(0x54000000L),
initBaudRate = BigInt(3686400L)))
nTxEntries = 256,
nRxEntries = 256))
})
class WithNICKey extends Config((site, here, up) => {
@ -49,14 +50,14 @@ class WithPerfCounters extends Config((site, here, up) => {
))
})
class BoomWithLargeTLBs extends Config((site, here, up) => {
/*class BoomWithLargeTLBs extends Config((site, here, up) => {
case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(
core = tile.core.copy(
nL2TLBEntries = 1024 // TLB reach = 1024 * 4KB = 4MB
)
))
})
*/
/*******************************************************************************
* Full TARGET_CONFIG configurations. These set parameters of the target being
@ -99,7 +100,7 @@ class FireSimRocketChipHexaCoreConfig extends Config(new WithNBigCores(6) ++
class FireSimRocketChipOctaCoreConfig extends Config(new WithNBigCores(8) ++
new FireSimRocketChipSingleCoreConfig)
/*
class FireSimBoomConfig extends Config(
new WithBootROM ++
new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
@ -110,4 +111,4 @@ class FireSimBoomConfig extends Config(
new WithBlockDevice ++
new BoomWithLargeTLBs ++
// Using a small config because it has 64-bit system bus, and compiles quickly
new boom.system.SmallBoomConfig)
new boom.system.SmallBoomConfig)*/

5
sim/src/main/scala/firesim/Targets.scala
View File

@ -4,7 +4,7 @@ import freechips.rocketchip._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.config.Parameters
import boom.system.{BoomSubsystem, BoomSubsystemModule}
/*import boom.system.{BoomSubsystem, BoomSubsystemModule}*/
import icenet._
import testchipip._
import sifive.blocks.devices.uart._
@ -71,7 +71,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod
with HasPeripheryBlockDeviceModuleImp
/*
class FireBoom(implicit p: Parameters) extends BoomSubsystem
with CanHaveMisalignedMasterAXI4MemPort
with HasPeripheryBootROM
@ -119,3 +119,4 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomSubsystemMod
with HasPeripherySerialModuleImp
with HasPeripheryUARTModuleImp
with HasPeripheryBlockDeviceModuleImp
*/

2
sw/firesim-software

@ -1 +1 @@
Subproject commit 334307a7e277a59f22d4ad10d530f23dae78bf07
Subproject commit 1eb154d9e237b2bb16952877caae5802cd3cfc66

4
target-design/TODO Normal file
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@ -0,0 +1,4 @@
-have not bumped riscv-tools
-have not fixed boom
-probably want to bump linux too
-barstools/mdf are not bumped to master

2
target-design/firechip

@ -1 +1 @@
Subproject commit 97153b5abe15ba1ad51ec8bda44b7f5ac6a876ad
Subproject commit 8d1b7425f37cd090db269f747c2757b01663d9c8