[SimMapping] Let blackboxes propogate through linking

2021-08-25 13:54:35 -07:00 · 2021-08-25 13:54:35 -07:00 · 7423958d5d
parent c7c514be9a
commit 7423958d5d
1 changed files with 1 additions and 2 deletions
--- a/sim/midas/src/main/scala/midas/passes/SimulationMapping.scala
+++ b/sim/midas/src/main/scala/midas/passes/SimulationMapping.scala
@ -74,8 +74,7 @@ private[passes] class SimulationMapping(targetName: String) extends firrtl.Trans
    case m: Module if m.name == targetBoxParent =>
      val body = initStmt(target, targetBoxInst)(m.body)
      Some(m.copy(info = info, body = body))
-    case m: Module => Some(m)
-    case m: ExtModule => None
+    case o => Some(o)
  }

  def execute(innerState: CircuitState) = {