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fix

This commit is contained in:
Sagar Karandikar 2020-02-09 01:05:38 +00:00
parent 685f3fdfeb
commit 7228b326c1
1 changed files with 3 additions and 3 deletions
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6
docs/Advanced-Usage/Debugging-and-Profiling-on-FPGA/TracerV.rst
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@ -179,8 +179,8 @@ when using TracerV under certain conditions:
* The number of cores/instruction streams is currently not automatically detected.
To collect data for multiple cores/instruction streams, you must change the
``NUM_CORES`` macro at the top of ``sim/firesim-lib/src/main/cc/bridges/tracerv.h``.
* TracerV currently packs the entire trace into a 512-bit word, so the maximum
supported value for ``NUM_CORES`` is 7. (7x 64-bit traces + a 64 bit cycle
number = 512 bits).
* TracerV currently packs the entire trace into a 512-bit word, so the maximum
supported value for ``NUM_CORES`` is 7. (7x 64-bit traces + a 64 bit cycle
number = 512 bits).
* Please reach out on the FireSim mailing list if you need help addressing any
of these restrictions: https://groups.google.com/forum/#!forum/firesim