Merge pull request #477 from firesim/fix-tracerv-cycle
[TracerV] Fix the reported target cycle
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commit
6dd3d1fd4f
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@ -156,11 +156,6 @@ class TracerVBridgeModule(key: TracerVKey)(implicit p: Parameters) extends Bridg
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triggerCycleCountEnd := hostTriggerCycleCountEnd
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val trace_cycle_counter = RegInit(0.U(64.W))
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when (tFire) {
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trace_cycle_counter := trace_cycle_counter + 1.U
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} .otherwise {
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trace_cycle_counter := trace_cycle_counter
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}
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//target instruction type trigger (trigger through target software)
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//can configure the trigger instruction type externally though simulation driver
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@ -226,14 +221,17 @@ class TracerVBridgeModule(key: TracerVKey)(implicit p: Parameters) extends Bridg
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0.U((outgoingPCISdat.io.enq.bits.getWidth - Cat(uint_traces).getWidth - trace_cycle_counter.getWidth).W)),
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Cat(uint_traces))
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val tFireHelper = DecoupledHelper(outgoingPCISdat.io.enq.ready,
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hPort.toHost.hValid, hPort.fromHost.hReady)
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hPort.fromHost.hValid := tFireHelper.fire(hPort.fromHost.hReady)
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hPort.toHost.hReady := tFireHelper.fire
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val tFireHelper = DecoupledHelper(outgoingPCISdat.io.enq.ready, hPort.toHost.hValid)
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hPort.toHost.hReady := tFireHelper.fire(hPort.toHost.hValid)
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// We don't drive tokens back to the target.
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hPort.fromHost.hValid := true.B
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outgoingPCISdat.io.enq.valid := tFireHelper.fire(outgoingPCISdat.io.enq.ready, trigger)
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when (tFireHelper.fire) {
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trace_cycle_counter := trace_cycle_counter + 1.U
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}
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// This need to go on a debug switch
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//when (outgoingPCISdat.io.enq.fire()) {
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// hPort.hBits.traces.zipWithIndex.foreach({ case (bundle, bIdx) =>
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