Remove GenericParameterizedBundle (not needed with new chisel)
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61ec026a98
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@ -2,7 +2,6 @@ package midas
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package models
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package models
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import org.chipsalliance.cde.config.Parameters
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import org.chipsalliance.cde.config.Parameters
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import freechips.rocketchip.util.GenericParameterizedBundle
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import chisel3._
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import chisel3._
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import chisel3.util._
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import chisel3.util._
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@ -345,7 +344,7 @@ class FirstReadyFCFSEntry(key: DRAMBaseConfig)(implicit p: Parameters) extends M
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// timing and resource constraints are met. The controller must also ensure CAS
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// timing and resource constraints are met. The controller must also ensure CAS
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// commands use the open ROW.
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// commands use the open ROW.
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class BankStateTrackerO(key: DramOrganizationParams) extends GenericParameterizedBundle(key)
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class BankStateTrackerO(val key: DramOrganizationParams) extends Bundle
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with CommandLegalBools {
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with CommandLegalBools {
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import DRAMMasEnums._
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import DRAMMasEnums._
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@ -355,7 +354,7 @@ class BankStateTrackerO(key: DramOrganizationParams) extends GenericParameterize
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def isRowHit(ref: MASEntry): Bool = ref.rowAddr === openRow && state === bank_active
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def isRowHit(ref: MASEntry): Bool = ref.rowAddr === openRow && state === bank_active
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}
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}
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class BankStateTrackerIO(val key: DramOrganizationParams) extends GenericParameterizedBundle(key)
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class BankStateTrackerIO(val key: DramOrganizationParams) extends Bundle
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with HasLegalityUpdateIO {
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with HasLegalityUpdateIO {
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val out = new BankStateTrackerO(key)
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val out = new BankStateTrackerO(key)
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val cmdUsesThisBank = Input(Bool())
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val cmdUsesThisBank = Input(Bool())
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@ -443,7 +442,7 @@ class BankStateTracker(key: DramOrganizationParams) extends Module with HasDRAMM
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// timing and resource constraints are met. The controller must also ensure CAS
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// timing and resource constraints are met. The controller must also ensure CAS
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// commands use the open ROW.
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// commands use the open ROW.
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class RankStateTrackerO(key: DramOrganizationParams) extends GenericParameterizedBundle(key)
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class RankStateTrackerO(val key: DramOrganizationParams) extends Bundle
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with CommandLegalBools {
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with CommandLegalBools {
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import DRAMMasEnums._
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import DRAMMasEnums._
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val canREF = Output(Bool())
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val canREF = Output(Bool())
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@ -452,7 +451,7 @@ class RankStateTrackerO(key: DramOrganizationParams) extends GenericParameterize
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val banks = Vec(key.maxBanks, Output(new BankStateTrackerO(key)))
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val banks = Vec(key.maxBanks, Output(new BankStateTrackerO(key)))
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}
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}
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class RankStateTrackerIO(val key: DramOrganizationParams) extends GenericParameterizedBundle(key)
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class RankStateTrackerIO(val key: DramOrganizationParams) extends Bundle
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with HasLegalityUpdateIO with HasDRAMMASConstants {
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with HasLegalityUpdateIO with HasDRAMMASConstants {
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val rank = new RankStateTrackerO(key)
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val rank = new RankStateTrackerO(key)
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val tCycle = Input(UInt(maxDRAMTimingBits.W))
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val tCycle = Input(UInt(maxDRAMTimingBits.W))
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@ -605,7 +604,7 @@ class CommandBusMonitor extends Module {
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}
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}
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}
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}
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class RankRefreshUnitIO(key: DramOrganizationParams) extends GenericParameterizedBundle(key) {
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class RankRefreshUnitIO(val key: DramOrganizationParams) extends Bundle {
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val rankStati = Vec(key.maxRanks, Flipped(new RankStateTrackerO(key)))
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val rankStati = Vec(key.maxRanks, Flipped(new RankStateTrackerO(key)))
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// The user may have instantiated multiple ranks, but is only modelling a single
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// The user may have instantiated multiple ranks, but is only modelling a single
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// rank system. Don't issue refreshes to ranks we aren't modelling
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// rank system. Don't issue refreshes to ranks we aren't modelling
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