replica
/
firesim
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

manager and file copying auto-ila

This commit is contained in:
alonamid 2018-09-07 22:44:52 +00:00
parent 9647905855
commit 6309ff87fc
2 changed files with 27 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
deploy/runtools/run_farm.py
View File

@ -343,6 +343,21 @@ class InstanceDeployManager:
with StreamLogger('stdout'), StreamLogger('stderr'):
run("sudo insmod /home/centos/edma/linux_kernel_drivers/edma/edma-drv.ko single_transaction_size=65536 transient_buffer_size=67108864 edma_queue_depth=1024 poll_mode=1")
def start_ila_server(self):
""" start the vivado hw_server and virtual jtag on simulation instance.) """
self.instance_logger("Starting Vivado hw_server.")
with StreamLogger('stdout'), StreamLogger('stderr'):
run("""screen -S hw_server -d -m bash -c "script -f -c '/opt/Xilinx/Vivado/2017.4.op/bin/hw_server'"; sleep 1""")
self.instance_logger("Starting Vivado virtual JTAG.")
with StreamLogger('stdout'), StreamLogger('stderr'):
run("""screen -S virtual_jtag -d -m bash -c "script -f -c 'sudo fpga-start-virtual-jtag -P 10201 -S 0'"; sleep 1""")
def kill_ila_server(self):
""" Kill the vivado hw_server and virtual jtag """
with warn_only(), StreamLogger('stdout'), StreamLogger('stderr'):
run("sudo pkill -SIGKILL hw_server")
with warn_only(), StreamLogger('stdout'), StreamLogger('stderr'):
run("sudo pkill -SIGKILL fpga-local-cmd")
def copy_sim_slot_infrastructure(self, slotno):
""" copy all the simulation infrastructure to the remote node. """
@ -446,6 +461,9 @@ class InstanceDeployManager:
# re-load EDMA
self.load_edma()
# start ila server
self.start_ila_server()
if self.instance_assigned_switches():
# all nodes could have a switch
for slotno in range(self.parentnode.get_num_switch_slots()):
@ -484,6 +502,7 @@ class InstanceDeployManager:
# only on sim nodes
for slotno in range(self.parentnode.get_num_fpga_slots_consumed()):
self.kill_sim_slot(slotno)
self.kill_ila_server()
def running_simulations(self):
""" collect screen results from node to see what's running on it. """

9
sim/Makefile
View File

@ -245,6 +245,7 @@ fpga_work_dir := $(board_dir)/cl_$(name_tuple)
build_dir := $(fpga_work_dir)/build
verif_dir := $(fpga_work_dir)/verif
fpga_v := $(fpga_work_dir)/design/cl_firesim_generated.sv
ila_work_dir := $(fpga_work_dir)/design/ila_files/
$(fpga_work_dir)/stamp: $(shell find $(board_dir)/cl_firesim -name '*')
mkdir -p $(@D)
@ -256,9 +257,15 @@ $(fpga_v): $(verilog) $(fpga_work_dir)/stamp
sed -i "s/\$$random/64'b0/g" $@
sed -i 's/fatal/fatal(0, "")/g' $@
.PHONY: $(ila_work_dir)
$(ila_work_dir): $(verilog) $(fpga_work_dir)/stamp
cp -f $(generated_dir)/firesim_ila_insert_* $(fpga_work_dir)/design/ila_files/
sed -i "s/\$$random/64'b0/g" $(fpga_work_dir)/design/ila_files/*
sed -i 's/fatal/fatal(0, "")/g' $(fpga_work_dir)/design/ila_files/*
# Goes as far as setting up the build directory without running the cad job
# Used by the manager before passing a build to a remote machine
replace-rtl: $(fpga_v)
replace-rtl: $(fpga_v) $(ila_work_dir)
.PHONY: replace-rtl
$(base_dir)/scripts/checkpoints/$(target_sim_tuple): $(fpga_work_dir)/stamp