Small cleanup
This commit is contained in:
abejgonzalez
parent
b0f60df9d6
commit
5fb2a23de6
|
|
@ -11,3 +11,5 @@ scala-doc-env.sh
|
|||
*.swp
|
||||
/.conda-env
|
||||
.metals
|
||||
vivado*.log
|
||||
vivado*.jou
|
||||
|
|
|
|||
|
|
@ -205,8 +205,10 @@ class F1BitBuilder(BitBuilder):
|
|||
Returns:
|
||||
Boolean indicating if the build passed or failed.
|
||||
"""
|
||||
build_farm = self.build_config.build_config_file.build_farm
|
||||
|
||||
if bypass:
|
||||
self.build_config.build_config_file.build_farm.release_build_host(self.build_config)
|
||||
build_farm.release_build_host(self.build_config)
|
||||
return True
|
||||
|
||||
# The default error-handling procedure. Send an email and teardown instance
|
||||
|
|
@ -222,7 +224,7 @@ class F1BitBuilder(BitBuilder):
|
|||
rootLogger.info(message_title)
|
||||
rootLogger.info(message_body)
|
||||
|
||||
self.build_config.build_config_file.build_farm.release_build_host(self.build_config)
|
||||
build_farm.release_build_host(self.build_config)
|
||||
|
||||
rootLogger.info("Building AWS F1 AGFI from Verilog")
|
||||
|
||||
|
|
@ -230,8 +232,6 @@ class F1BitBuilder(BitBuilder):
|
|||
fpga_build_postfix = f"hdk/cl/developer_designs/cl_{self.build_config.get_chisel_quintuplet()}"
|
||||
local_results_dir = f"{local_deploy_dir}/results-build/{self.build_config.get_build_dir_name()}"
|
||||
|
||||
build_farm = self.build_config.build_config_file.build_farm
|
||||
|
||||
# 'cl_dir' holds the eventual directory in which vivado will run.
|
||||
cl_dir = self.cl_dir_setup(self.build_config.get_chisel_quintuplet(), build_farm.get_build_host(self.build_config).dest_build_dir)
|
||||
|
||||
|
|
@ -271,7 +271,7 @@ class F1BitBuilder(BitBuilder):
|
|||
on_build_failure()
|
||||
return False
|
||||
|
||||
self.build_config.build_config_file.build_farm.release_build_host(self.build_config)
|
||||
build_farm.release_build_host(self.build_config)
|
||||
|
||||
return True
|
||||
|
||||
|
|
@ -431,8 +431,10 @@ class VitisBitBuilder(BitBuilder):
|
|||
Returns:
|
||||
Boolean indicating if the build passed or failed.
|
||||
"""
|
||||
build_farm = self.build_config.build_config_file.build_farm
|
||||
|
||||
if bypass:
|
||||
self.build_config.build_config_file.build_farm.release_build_host(self.build_config)
|
||||
build_farm.release_build_host(self.build_config)
|
||||
return True
|
||||
|
||||
# The default error-handling procedure. Send an email and teardown instance
|
||||
|
|
@ -446,7 +448,7 @@ class VitisBitBuilder(BitBuilder):
|
|||
rootLogger.info(message_title)
|
||||
rootLogger.info(message_body)
|
||||
|
||||
self.build_config.build_config_file.build_farm.release_build_host(self.build_config)
|
||||
build_farm.release_build_host(self.build_config)
|
||||
|
||||
rootLogger.info("Building Vitis Bitstream from Verilog")
|
||||
|
||||
|
|
@ -454,8 +456,6 @@ class VitisBitBuilder(BitBuilder):
|
|||
fpga_build_postfix = f"cl_{self.build_config.get_chisel_quintuplet()}"
|
||||
local_results_dir = f"{local_deploy_dir}/results-build/{self.build_config.get_build_dir_name()}"
|
||||
|
||||
build_farm = self.build_config.build_config_file.build_farm
|
||||
|
||||
# 'cl_dir' holds the eventual directory in which vivado will run.
|
||||
cl_dir = self.cl_dir_setup(self.build_config.get_chisel_quintuplet(), build_farm.get_build_host(self.build_config).dest_build_dir)
|
||||
|
||||
|
|
@ -489,9 +489,6 @@ class VitisBitBuilder(BitBuilder):
|
|||
on_build_failure()
|
||||
return False
|
||||
|
||||
build_farm = self.build_config.build_config_file.build_farm
|
||||
hostname = build_farm.get_build_host_ip(self.build_config)
|
||||
|
||||
hwdb_entry_name = self.build_config.name
|
||||
local_cl_dir = f"{local_results_dir}/{fpga_build_postfix}"
|
||||
xclbin_path = "file://" + local_cl_dir + f"/bitstream/build_dir.{self.device}/firesim.xclbin"
|
||||
|
|
@ -522,7 +519,7 @@ class VitisBitBuilder(BitBuilder):
|
|||
|
||||
rootLogger.info(f"Build complete! Vitis bitstream ready. See {os.path.join(hwdb_entry_file_location,hwdb_entry_name)}.")
|
||||
|
||||
self.build_config.build_config_file.build_farm.release_build_host(self.build_config)
|
||||
build_farm.release_build_host(self.build_config)
|
||||
|
||||
return True
|
||||
|
||||
|
|
@ -587,8 +584,10 @@ class XilinxAlveoBitBuilder(BitBuilder):
|
|||
Returns:
|
||||
Boolean indicating if the build passed or failed.
|
||||
"""
|
||||
build_farm = self.build_config.build_config_file.build_farm
|
||||
|
||||
if bypass:
|
||||
self.build_config.build_config_file.build_farm.release_build_host(self.build_config)
|
||||
build_farm.release_build_host(self.build_config)
|
||||
return True
|
||||
|
||||
# The default error-handling procedure. Send an email and teardown instance
|
||||
|
|
@ -602,7 +601,7 @@ class XilinxAlveoBitBuilder(BitBuilder):
|
|||
rootLogger.info(message_title)
|
||||
rootLogger.info(message_body)
|
||||
|
||||
self.build_config.build_config_file.build_farm.release_build_host(self.build_config)
|
||||
build_farm.release_build_host(self.build_config)
|
||||
|
||||
rootLogger.info(f"Building Xilinx Alveo {self.build_config.PLATFORM} Bitstream from Verilog")
|
||||
|
||||
|
|
@ -610,8 +609,6 @@ class XilinxAlveoBitBuilder(BitBuilder):
|
|||
fpga_build_postfix = f"cl_{self.build_config.get_chisel_quintuplet()}"
|
||||
local_results_dir = f"{local_deploy_dir}/results-build/{self.build_config.get_build_dir_name()}"
|
||||
|
||||
build_farm = self.build_config.build_config_file.build_farm
|
||||
|
||||
# 'cl_dir' holds the eventual directory in which vivado will run.
|
||||
cl_dir = self.cl_dir_setup(self.build_config.get_chisel_quintuplet(), build_farm.get_build_host(self.build_config).dest_build_dir)
|
||||
|
||||
|
|
@ -667,9 +664,6 @@ class XilinxAlveoBitBuilder(BitBuilder):
|
|||
with prefix(f"cd {local_cl_dir}"):
|
||||
local(f"tar zcvf {tar_name} {self.build_config.PLATFORM}/")
|
||||
|
||||
build_farm = self.build_config.build_config_file.build_farm
|
||||
hostname = build_farm.get_build_host_ip(self.build_config)
|
||||
|
||||
hwdb_entry = hwdb_entry_name + ":\n"
|
||||
hwdb_entry += f" bitstream_tar: file://{local_cl_dir}/{tar_name}\n"
|
||||
hwdb_entry += f" deploy_quintuplet_override: null\n"
|
||||
|
|
@ -696,7 +690,7 @@ class XilinxAlveoBitBuilder(BitBuilder):
|
|||
|
||||
rootLogger.info(f"Build complete! Xilinx Alveo {self.build_config.PLATFORM} bitstream ready. See {os.path.join(hwdb_entry_file_location,hwdb_entry_name)}.")
|
||||
|
||||
self.build_config.build_config_file.build_farm.release_build_host(self.build_config)
|
||||
build_farm.release_build_host(self.build_config)
|
||||
|
||||
return True
|
||||
|
||||
|
|
|
|||
|
|
@ -155,7 +155,7 @@ class URIContainer:
|
|||
class RuntimeHWConfig:
|
||||
""" A pythonic version of the entires in config_hwdb.yaml """
|
||||
name: str
|
||||
platform: Optional[str] = None
|
||||
platform: Optional[str]
|
||||
|
||||
# TODO: should be abstracted out between platforms with a URI
|
||||
agfi: Optional[str]
|
||||
|
|
@ -167,10 +167,10 @@ class RuntimeHWConfig:
|
|||
deploy_quintuplet: Optional[str]
|
||||
customruntimeconfig: str
|
||||
# note whether we've built a copy of the simulation driver for this hwconf
|
||||
driver_built: bool = False
|
||||
tarball_built: bool = False
|
||||
additional_required_files: List[Tuple[str, str]] = []
|
||||
driver_name_prefix: str = ""
|
||||
driver_built: bool
|
||||
tarball_built: bool
|
||||
additional_required_files: List[Tuple[str, str]]
|
||||
driver_name_prefix: str
|
||||
driver_name_suffix: Optional[str]
|
||||
local_driver_base_dir: str = LOCAL_DRIVERS_BASE
|
||||
driver_type_message: str = "FPGA software"
|
||||
|
|
@ -193,6 +193,12 @@ class RuntimeHWConfig:
|
|||
self.bitstream_tar = hwconfig_dict.get('bitstream_tar')
|
||||
self.driver_tar = hwconfig_dict.get('driver_tar')
|
||||
|
||||
self.platform = None
|
||||
self.driver_built = False
|
||||
self.tarball_built = False
|
||||
self.additional_required_files = []
|
||||
self.driver_name_prefix = ""
|
||||
|
||||
self.uri_list = []
|
||||
|
||||
if self.agfi is not None:
|
||||
|
|
@ -234,6 +240,11 @@ class RuntimeHWConfig:
|
|||
|
||||
self.uri_list.append(URIContainer('driver_tar', self.get_driver_tar_filename()))
|
||||
|
||||
def get_deploytriplet_for_config(self) -> str:
|
||||
""" Get the deploytriplet for this configuration. """
|
||||
quin = self.get_deployquintuplet_for_config()
|
||||
return "-".join(quin.split("-")[2:])
|
||||
|
||||
@classmethod
|
||||
def get_driver_tar_filename(cls) -> str:
|
||||
""" Get the name of the tarball inside the sim_slot_X directory on the run host. """
|
||||
|
|
@ -283,11 +294,6 @@ class RuntimeHWConfig:
|
|||
|
||||
return self.deploy_quintuplet
|
||||
|
||||
def get_deploytriplet_for_config(self) -> str:
|
||||
""" Get the deploytriplet for this configuration. """
|
||||
quin = self.get_deployquintuplet_for_config()
|
||||
return "-".join(quin.split("-")[2:])
|
||||
|
||||
def get_design_name(self) -> str:
|
||||
""" Returns the name used to prefix MIDAS-emitted files. (The DESIGN make var) """
|
||||
return self.get_deployquintuplet_for_config().split("-")[1]
|
||||
|
|
|
|||
|
|
@ -57,19 +57,19 @@ firesim_gemmini_rocket_singlecore_no_nic:
|
|||
custom_runtime_config: null
|
||||
vitis_firesim_rocket_singlecore_no_nic:
|
||||
xclbin: https://firesim-ci-vitis-xclbins.s3.us-west-2.amazonaws.com/vitis_firesim_rocket_singlecore_no_nic_c12936.xclbin
|
||||
deploy_quintuplet_override: firesim-FireSim-FireSimRocketMMIOOnlyConfig-BaseVitisConfig
|
||||
deploy_quintuplet_override: vitis-firesim-FireSim-FireSimRocketMMIOOnlyConfig-BaseVitisConfig
|
||||
custom_runtime_config: null
|
||||
vitis_firesim_gemmini_rocket_singlecore_no_nic:
|
||||
xclbin: https://firesim-ci-vitis-xclbins.s3.us-west-2.amazonaws.com/vitis_firesim_gemmini_rocket_singlecore_no_nic_1ea5c4.xclbin
|
||||
deploy_quintuplet_override: firesim-FireSim-FireSimLeanGemminiRocketMMIOOnlyConfig-BaseVitisConfig
|
||||
deploy_quintuplet_override: vitis-firesim-FireSim-FireSimLeanGemminiRocketMMIOOnlyConfig-BaseVitisConfig
|
||||
custom_runtime_config: null
|
||||
# DOCREF START: Xilinx Alveo HWDB Entries
|
||||
alveo_u250_firesim_rocket_singlecore_no_nic:
|
||||
bitstream_tar: REPLACE_THIS
|
||||
deploy_quintuplet_override: firesim-FireSim-FireSimRocketConfig-BaseXilinxAlveoConfig
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
alveo_u280_firesim_rocket_singlecore_no_nic:
|
||||
bitstream_tar: REPLACE_THIS
|
||||
deploy_quintuplet_override: firesim-FireSim-FireSimRocketConfig-BaseXilinxAlveoConfig
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
# DOCREF END: Xilinx Alveo HWDB Entries
|
||||
|
|
|
|||
|
|
@ -216,7 +216,7 @@ To generate a specific instance of a target, the build system leverages five Mak
|
|||
|
||||
5. ``PLATFORM``: this points the Makefile (`sim/Makefile`) at the right
|
||||
FPGA platform to build for. This must correspond to a platform
|
||||
defined at ``platforms/``.
|
||||
defined at :gh-file-ref:`platforms`.
|
||||
|
||||
``TARGET_CONFIG`` and ``PLATFORM_CONFIG`` are strings that are used to construct a
|
||||
``Config`` instance (derives from RocketChip's parameterization system, ``Config``, see the
|
||||
|
|
|
|||
|
|
@ -413,7 +413,7 @@ Specifies the host FPGA frequency for a bitstream build.
|
|||
|
||||
Specifies a pre-canned set of strategies and directives to pass to the
|
||||
bitstream build. Note, these are implemented differently on different host
|
||||
platforms, but try to optimize for the same things. Strategies supported across both Vitis, Xilinx Alveo U250, and EC2 F1 include:
|
||||
platforms, but try to optimize for the same things. Strategies supported across both Vitis, Xilinx Alveo U250/U280, and EC2 F1 include:
|
||||
|
||||
- ``TIMING``: Optimize for improved fmax.
|
||||
- ``AREA``: Optimize for reduced resource utilization.
|
||||
|
|
@ -441,7 +441,7 @@ in greater detail :ref:`here<generating-different-targets>`). If
|
|||
""""""""""""""""""""""""""
|
||||
|
||||
This allows you to override the ``deployquintuplet`` stored with the AGFI.
|
||||
Otherwise, the ``PLATFORM`` / TARGET_PROJECT``/``DESIGN``/``TARGET_CONFIG``/``PLATFORM_CONFIG`` you specify
|
||||
Otherwise, the ``PLATFORM``/``TARGET_PROJECT``/``DESIGN``/``TARGET_CONFIG``/``PLATFORM_CONFIG`` you specify
|
||||
above will be used. See the AGFI Tagging section for more details. Most likely,
|
||||
you should leave this set to ``null``. This is usually only used if you have
|
||||
proprietary RTL that you bake into an FPGA image, but don't want to share with
|
||||
|
|
@ -533,10 +533,10 @@ Indicates where the bitstream (FPGA Image) is located, may be one of:
|
|||
* A Uniform Resource Identifier (URI), (see :ref:`uri-path-support` for details)
|
||||
* A filesystem path available to the manager. Local paths are relative to the `deploy` folder.
|
||||
|
||||
``bit``
|
||||
``bitstream_tar``
|
||||
"""""""""""""""
|
||||
|
||||
Indicates where the bitstream (FPGA Image) is located, may be one of:
|
||||
Indicates where the bitstream (FPGA Image) and metadata associated with it is located, may be one of:
|
||||
* A Uniform Resource Identifier (URI), (see :ref:`uri-path-support` for details)
|
||||
* A filesystem path available to the manager. Local paths are relative to the `deploy` folder.
|
||||
|
||||
|
|
@ -752,7 +752,7 @@ simulations across all run farm hosts.
|
|||
For example, this class manages how to flash FPGAs with bitstreams, how to copy back results, and how to check if a simulation is running.
|
||||
By default, deploy platform classes can be found in :gh-file-ref:`deploy/runtools/run_farm_deploy_managers.py`. However, you can specify
|
||||
your own custom run farm classes by adding your python file to the ``PYTHONPATH``.
|
||||
There are default deploy managers / platforms that correspond to AWS EC2 F1 FPGAs, Vitis FPGAs, and Xilinx Alveo U250 FPGAs, ``EC2InstanceDeployManager``, ``VitisInstanceDeployManager``, ``XilinxAlveoU250InstanceDeployManager``, respectively.
|
||||
There are default deploy managers / platforms that correspond to AWS EC2 F1 FPGAs, Vitis FPGAs, and Xilinx Alveo U250/U280 FPGAs, ``EC2InstanceDeployManager``, ``VitisInstanceDeployManager``, ``XilinxAlveo{U250,U280}InstanceDeployManager``, respectively.
|
||||
For example, to use the ``EC2InstanceDeployManager`` deploy platform class, you would write ``default_platform: EC2InstanceDeployManager``.
|
||||
|
||||
``default_simulation_dir``
|
||||
|
|
@ -945,7 +945,7 @@ This bit builder recipe configures a build farm host to build an Vitis bitstream
|
|||
|
||||
``device``
|
||||
""""""""""""""""""""""""""
|
||||
This specifies a Vitis platform to compile against, for example: ``xilinx_u250_gen3x16_xdma_3_1_202020_1`` when targeting a Alveo U250 FPGA.
|
||||
This specifies a Vitis platform to compile against, for example: ``xilinx_u250_gen3x16_xdma_3_1_202020_1`` when targeting a Vitis-enabled Alveo U250 FPGA.
|
||||
|
||||
Here is an example of this configuration file:
|
||||
|
||||
|
|
|
|||
|
|
@ -82,7 +82,7 @@ For each config, the build process entails:
|
|||
7. [Local or Remote] Run Vitis Synthesis and P&R for the configuration
|
||||
8. [Local/Remote] Copy back all output generated by Vitis (including ``xclbin`` bitstream)
|
||||
|
||||
.. tab:: Xilinx Alveo U250
|
||||
.. tab:: Xilinx Alveo U250/U280
|
||||
|
||||
1. [Locally] Run the elaboration process for your hardware configuration
|
||||
2. [Locally] FAME-1 transform the design with MIDAS
|
||||
|
|
@ -119,10 +119,10 @@ This directory will contain:
|
|||
This contains reports, ``stdout`` from the build, and the final bitstream ``xclbin`` file produced by Vitis.
|
||||
This also contains a copy of the generated verilog (``FireSim-generated.sv``) used to produce this build.
|
||||
|
||||
.. tab:: Xilinx Alveo U250
|
||||
.. tab:: Xilinx Alveo U250/U280
|
||||
|
||||
The Vivado project collateral that built the FPGA image, in the state it was in when the Vivado build process completed.
|
||||
This contains reports, ``stdout`` from the build, and the final bitstream ``bit`` file produced by Vivado.
|
||||
This contains reports, ``stdout`` from the build, and the final ``bitstream_tar`` bitstream/metadata file produced by Vivado.
|
||||
This also contains a copy of the generated verilog (``FireSim-generated.sv``) used to produce this build.
|
||||
|
||||
If this command is cancelled by a SIGINT, it will prompt for confirmation
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ The Supernode target configuration wrapper can be found in Chipyard in
|
|||
``chipyard/generators/firechip/src/main/scala/TargetConfigs.scala``. An example wrapper
|
||||
configuration is:
|
||||
|
||||
.. code-block:: python
|
||||
.. code-block:: scala
|
||||
|
||||
class SupernodeFireSimRocketConfig extends Config(
|
||||
new WithNumNodes(4) ++
|
||||
|
|
@ -48,7 +48,7 @@ different target configuration, we will generate a new supernode wrapper, with
|
|||
the new target configuration. For example, to simulate 4 quad-core nodes on one
|
||||
FPGA, you can use:
|
||||
|
||||
.. code-block:: python
|
||||
.. code-block:: scala
|
||||
|
||||
class SupernodeFireSimQuadRocketConfig extends Config(
|
||||
new WithNumNodes(4) ++
|
||||
|
|
|
|||
|
|
@ -125,10 +125,10 @@ Get Started
|
|||
FireSim supports many type of FPGAs and FPGA platforms!
|
||||
Click one of the following links to get started with your particular platform.
|
||||
|
||||
* Reference to AWS EC2 F1
|
||||
* :doc:`/Getting-Started-Guides/AWS-EC2-F1-Tutorial/index`
|
||||
|
||||
* Reference to On Premises Intro
|
||||
* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Tutorial/Xilinx-Alveo-U250-FPGAs`
|
||||
|
||||
* Reference to Xilinx Alveo U250
|
||||
* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Tutorial/Xilinx-Alveo-U280-FPGAs`
|
||||
|
||||
* Reference to Xilinx Alveo U280
|
||||
* :doc:`Getting-Started-Guides/On-Premises-FPGA-Tutorial/Xilinx-Vitis-FPGAs`
|
||||
|
|
|
|||
|
|
@ -3,6 +3,6 @@
|
|||
.. |deploy_manager_code| replace:: ``XilinxAlveoU250InstanceDeployManager``
|
||||
.. |runner| replace:: Xilinx Vivado
|
||||
.. |hwdb_entry| replace:: alveo_u250_firesim_rocket_singlecore_no_nic
|
||||
.. |quintuplet| replace:: FireSim-FireSimRocketConfig-BaseXilinxAlveoConfig
|
||||
.. |quintuplet| replace:: xilinx_alveo_u250-firesim-FireSim-FireSimRocketConfig-BaseXilinxAlveoConfig
|
||||
|
||||
.. include:: Running-Single-Node-Simulation-Template.rst
|
||||
|
|
|
|||
|
|
@ -3,6 +3,6 @@
|
|||
.. |deploy_manager_code| replace:: ``XilinxAlveoU280InstanceDeployManager``
|
||||
.. |runner| replace:: Xilinx Vivado
|
||||
.. |hwdb_entry| replace:: alveo_u280_firesim_rocket_singlecore_no_nic
|
||||
.. |quintuplet| replace:: FireSim-FireSimRocketConfig-BaseXilinxAlveoConfig
|
||||
.. |quintuplet| replace:: xilinx_alveo_u280-firesim-FireSim-FireSimRocketConfig-BaseXilinxAlveoConfig
|
||||
|
||||
.. include:: Running-Single-Node-Simulation-Template.rst
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
.. |deploy_manager_code| replace:: ``VitisInstanceDeployManager``
|
||||
.. |runner| replace:: Xilinx XRT/Vitis
|
||||
.. |hwdb_entry| replace:: vitis_firesim_rocket_singlecore_no_nic
|
||||
.. |quintuplet| replace:: FireSim-FireSimRocketConfig-BaseVitisConfig
|
||||
.. |quintuplet| replace:: vitis-firesim-FireSim-FireSimRocketConfig-BaseVitisConfig
|
||||
|
||||
.. include:: Running-Single-Node-Simulation-Template.rst
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue