From 1654f7970cda002bd443e730170c7560847cc551 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 5 Jun 2023 21:29:17 -0700 Subject: [PATCH 1/2] TracerV: restore old trigger credit / debit timing --- .../main/scala/bridges/TracerVBridge.scala | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/sim/firesim-lib/src/main/scala/bridges/TracerVBridge.scala b/sim/firesim-lib/src/main/scala/bridges/TracerVBridge.scala index c8eacb61..c705cf78 100644 --- a/sim/firesim-lib/src/main/scala/bridges/TracerVBridge.scala +++ b/sim/firesim-lib/src/main/scala/bridges/TracerVBridge.scala @@ -201,14 +201,6 @@ class TracerVBridgeModule(key: TraceBundleWidths)(implicit p: Parameters) ), ) - val tFireHelper = DecoupledHelper(streamEnq.ready, hPort.toHost.hValid, hPort.fromHost.hReady, initDone) - - val triggerReg = RegEnable(trigger, false.B, tFireHelper.fire()) - hPort.hBits.triggerDebit := !trigger && triggerReg - hPort.hBits.triggerCredit := trigger && !triggerReg - - hPort.fromHost.hValid := tFireHelper.fire(hPort.fromHost.hReady) - // the maximum width of a single arm, this is determined by the 512 bit width of a single beat val armWidth = 7 @@ -247,8 +239,8 @@ class TracerVBridgeModule(key: TraceBundleWidths)(implicit p: Parameters) val maybeFire = !anyValidRemainMux || (counter === (armCount - 1).U) val maybeEnq = anyValidRemainMux - val do_enq_helper = DecoupledHelper(hPort.toHost.hValid, streamEnq.ready, maybeEnq, traceEnable) - val do_fire_helper = DecoupledHelper(hPort.toHost.hValid, streamEnq.ready, maybeFire) + val do_enq_helper = DecoupledHelper(hPort.toHost.hValid, hPort.fromHost.hReady, streamEnq.ready, maybeEnq, traceEnable) + val do_fire_helper = DecoupledHelper(hPort.toHost.hValid, hPort.fromHost.hReady, streamEnq.ready, maybeFire) // Note, if we dequeue a token that wins out over the increment below when(do_fire_helper.fire()) { @@ -260,6 +252,13 @@ class TracerVBridgeModule(key: TraceBundleWidths)(implicit p: Parameters) streamEnq.valid := do_enq_helper.fire(streamEnq.ready, trigger) hPort.toHost.hReady := do_fire_helper.fire(hPort.toHost.hValid) + // Output token (back to hub model) handling. + val triggerReg = RegEnable(trigger, false.B, do_fire_helper.fire()) + hPort.hBits.triggerDebit := !trigger && triggerReg + hPort.hBits.triggerCredit := trigger && !triggerReg + + hPort.fromHost.hValid := do_fire_helper.fire(hPort.fromHost.hReady) + when(hPort.toHost.fire) { trace_cycle_counter := trace_cycle_counter + 1.U } From 073b62254d8d0e1de664352f0518903f5b4a32e9 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 5 Jun 2023 21:49:22 -0700 Subject: [PATCH 2/2] Add initDone back in --- sim/firesim-lib/src/main/scala/bridges/TracerVBridge.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/sim/firesim-lib/src/main/scala/bridges/TracerVBridge.scala b/sim/firesim-lib/src/main/scala/bridges/TracerVBridge.scala index c705cf78..23d864a9 100644 --- a/sim/firesim-lib/src/main/scala/bridges/TracerVBridge.scala +++ b/sim/firesim-lib/src/main/scala/bridges/TracerVBridge.scala @@ -239,8 +239,9 @@ class TracerVBridgeModule(key: TraceBundleWidths)(implicit p: Parameters) val maybeFire = !anyValidRemainMux || (counter === (armCount - 1).U) val maybeEnq = anyValidRemainMux - val do_enq_helper = DecoupledHelper(hPort.toHost.hValid, hPort.fromHost.hReady, streamEnq.ready, maybeEnq, traceEnable) - val do_fire_helper = DecoupledHelper(hPort.toHost.hValid, hPort.fromHost.hReady, streamEnq.ready, maybeFire) + val commonPredicates = Seq(hPort.toHost.hValid, hPort.fromHost.hReady, streamEnq.ready, initDone) + val do_enq_helper = DecoupledHelper((Seq(maybeEnq, traceEnable) ++ commonPredicates):_*) + val do_fire_helper = DecoupledHelper((maybeFire +: commonPredicates):_*) // Note, if we dequeue a token that wins out over the increment below when(do_fire_helper.fire()) {