UART Bridge test (#1326)
Added a UART test in a new group of tests, 'bridges'. This test group includes the bridges from firesim-lib, which rely on more external dependencies. The previous `midasexamples` test suite is limited to simple tests with no dependencies.
This commit is contained in:
Nandor Licker
GitHub
parent
b3c39d171a
commit
5434084309
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@ -267,9 +267,22 @@ jobs:
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with:
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test-name: "CIGroupB"
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run-test-firesim-lib:
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name: run-test-firesim-lib
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needs: [run-test-groupB]
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runs-on: aws-${{ github.run_id }}
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env:
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TERM: xterm-256-color
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steps:
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- uses: actions/checkout@v3
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- name: Run firesim-lib Scala tests
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uses: ./.github/actions/run-scala-test
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with:
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test-name: "BridgeTests"
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run-chipyard-tests:
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name: run-chipyard-tests
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needs: [run-test-groupB]
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needs: [run-test-firesim-lib]
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runs-on: aws-${{ github.run_id }}
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env:
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TERM: xterm-256-color
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@ -171,7 +171,9 @@ resides in ``sim/``. These projects are:
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:gh-file-ref:`sim/src/main/scala/midasexamples`, these are a set of simple chisel
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circuits like GCD, that demonstrate how to use Golden Gate. These are useful test
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cases for bringing up new Golden Gate features.
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3. **fasedtests**: designs to do integration testing of FASED memory-system timing models.
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3. **bridges**: tests for firesim-lib bridges. These have more dependencies and
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involve more logic than `midasexamples`.
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4. **fasedtests**: designs to do integration testing of FASED memory-system timing models.
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Projects have the following directory structure:
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@ -42,10 +42,7 @@ void sighand(int s) {
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}
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#endif
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uart_t::uart_t(simif_t *sim,
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const UARTBRIDGEMODULE_struct &mmio_addrs,
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int uartno)
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: bridge_driver_t(sim), mmio_addrs(mmio_addrs) {
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uart_fd_handler::uart_fd_handler(int uartno) {
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this->loggingfd = 0; // unused
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if (uartno == 0) {
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@ -92,7 +89,42 @@ uart_t::uart_t(simif_t *sim,
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fcntl(inputfd, F_SETFL, fcntl(inputfd, F_GETFL) | O_NONBLOCK);
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}
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uart_t::~uart_t() { close(this->loggingfd); }
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uart_fd_handler::~uart_fd_handler() { close(this->loggingfd); }
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std::optional<char> uart_fd_handler::get() {
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char inp;
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int readamt;
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if (specialchar) {
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// send special character (e.g. ctrl-c)
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// for stdin handling
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//
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// PTY should never trigger this
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inp = specialchar;
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specialchar = 0;
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readamt = 1;
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} else {
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// else check if we have input
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readamt = ::read(inputfd, &inp, 1);
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}
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if (readamt <= 0)
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return std::nullopt;
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return inp;
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}
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void uart_fd_handler::put(char data) {
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::write(outputfd, &data, 1);
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if (loggingfd) {
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::write(loggingfd, &data, 1);
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}
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}
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uart_t::uart_t(simif_t *sim,
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const UARTBRIDGEMODULE_struct &mmio_addrs,
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int uartno)
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: uart_t(sim, mmio_addrs, std::make_unique<uart_fd_handler>(uartno)) {}
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uart_t::~uart_t() {}
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void uart_t::send() {
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if (data.in.fire()) {
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@ -119,32 +151,14 @@ void uart_t::tick() {
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this->recv();
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if (data.in.ready) {
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char inp;
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int readamt;
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if (specialchar) {
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// send special character (e.g. ctrl-c)
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// for stdin handling
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//
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// PTY should never trigger this
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inp = specialchar;
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specialchar = 0;
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readamt = 1;
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} else {
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// else check if we have input
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readamt = ::read(inputfd, &inp, 1);
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}
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if (readamt > 0) {
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data.in.bits = inp;
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if (auto bits = handler->get()) {
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data.in.bits = *bits;
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data.in.valid = true;
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}
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}
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if (data.out.fire()) {
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::write(outputfd, &data.out.bits, 1);
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if (loggingfd) {
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::write(loggingfd, &data.out.bits, 1);
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}
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handler->put(data.out.bits);
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}
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this->send();
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@ -2,9 +2,11 @@
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#ifndef __UART_H
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#define __UART_H
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#include "serial.h"
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#include <optional>
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#include <signal.h>
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#include "serial.h"
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// The definition of the primary constructor argument for a bridge is generated
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// by Golden Gate at compile time _iff_ the bridge is instantiated in the
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// target. As a result, all bridge driver definitions conditionally remove
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@ -15,28 +17,68 @@
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// all-caps, suffixed with "_struct" and "_struct_guard" respectively.
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#ifdef UARTBRIDGEMODULE_struct_guard
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class uart_t : public bridge_driver_t {
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/**
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* Base class for callbacks handling data coming in and out a UART stream.
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*/
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class uart_handler {
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public:
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virtual ~uart_handler() {}
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virtual std::optional<char> get() = 0;
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virtual void put(char data) = 0;
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};
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/**
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* Helper class which links the UART stream to either a file or PTY.
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*/
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class uart_fd_handler final : public uart_handler {
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public:
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uart_fd_handler(int uartno);
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~uart_fd_handler();
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std::optional<char> get() override;
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void put(char data) override;
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private:
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int inputfd;
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int outputfd;
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int loggingfd;
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};
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class uart_t final : public bridge_driver_t {
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public:
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/// Creates a bridge which interacts with standard streams or PTY.
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uart_t(simif_t *sim, const UARTBRIDGEMODULE_struct &mmio_addrs, int uartno);
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/// Creates a bridge which pulls/pushes data using a custom handler.
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uart_t(simif_t *sim,
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const UARTBRIDGEMODULE_struct &mmio_addrs,
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std::unique_ptr<uart_handler> &&handler)
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: bridge_driver_t(sim), mmio_addrs(mmio_addrs),
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handler(std::move(handler)) {}
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~uart_t();
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virtual void tick();
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void tick();
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// Our UART bridge's initialzation and teardown procedures don't
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// require interaction with the FPGA (i.e., MMIO), and so we don't need
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// to define init and finish methods (we can do everything in the
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// ctor/dtor)
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virtual void init(){};
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virtual void finish(){};
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void init(){};
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void finish(){};
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// Our UART bridge never calls for the simulation to terminate
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virtual bool terminate() { return false; }
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bool terminate() { return false; }
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// ... and thus, never returns a non-zero exit code
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virtual int exit_code() { return 0; }
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int exit_code() { return 0; }
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private:
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const UARTBRIDGEMODULE_struct mmio_addrs;
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serial_data_t<char> data;
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int inputfd;
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int outputfd;
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int loggingfd;
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std::unique_ptr<uart_handler> handler;
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void send();
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void recv();
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};
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@ -0,0 +1,84 @@
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// See LICENSE for license details.
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#ifndef RTLSIM
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#include "simif_f1.h"
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#define SIMIF simif_f1_t
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#else
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#include "simif_emul.h"
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#define SIMIF simif_emul_t
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#endif
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#include "bridges/uart.h"
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#include "simif_peek_poke.h"
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class UARTModuleTest final : public simif_peek_poke_t {
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public:
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class Handler final : public uart_handler {
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public:
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Handler(UARTModuleTest &test) { test.handler = this; }
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~Handler() {
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// Check that the input and output buffers are equal.
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if (in_buffer != out_buffer) {
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fprintf(stderr,
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"Buffer mismatch:\n %s\n %s\n",
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in_buffer.c_str(),
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out_buffer.c_str());
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abort();
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}
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}
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std::optional<char> get() override {
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if (in_index >= in_buffer.size())
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return std::nullopt;
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return in_buffer[in_index++];
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}
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void put(char data) override { out_buffer += data; }
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const std::string in_buffer = "We are testing the UART bridge";
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std::string out_buffer;
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size_t in_index = 0;
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};
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Handler *handler;
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UARTModuleTest(simif_t &simif)
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: simif_peek_poke_t(&simif, PEEKPOKEBRIDGEMODULE_0_substruct_create),
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uart(std::make_unique<uart_t>(&simif,
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UARTBRIDGEMODULE_0_substruct_create,
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std::make_unique<Handler>(*this))) {}
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void run() {
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// Initialise the UART bridge.
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uart->init();
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// Reset the device.
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poke(reset, 1);
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step(1);
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poke(reset, 0);
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step(1);
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// Tick until the out buffer is filled in.
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step(300000, false);
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for (unsigned i = 0; i < 100000 && !simif->done(); ++i) {
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uart->tick();
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}
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// Cleanup.
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uart->finish();
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}
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private:
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std::unique_ptr<uart_t> uart;
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};
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int main(int argc, char **argv) {
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std::vector<std::string> args(argv + 1, argv + argc);
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SIMIF simif(args);
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simif.init(argc, argv);
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UARTModuleTest test(simif);
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test.run();
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return test.teardown();
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}
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@ -0,0 +1,110 @@
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# See LICENSE for license details.
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# These point at the main class of the target's Chisel generator
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DESIGN_PACKAGE ?= firesim.bridges
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DESIGN ?= GCD
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TARGET_CONFIG_PACKAGE ?= firesim.bridges
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TARGET_CONFIG ?= NoConfig
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PLATFORM_CONFIG_PACKAGE ?= firesim.bridges
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PLATFORM_CONFIG ?= DefaultF1Config
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name_tuple := $(DESIGN)-$(TARGET_CONFIG)-$(PLATFORM_CONFIG)
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GENERATED_DIR := $(firesim_base_dir)/generated-src/$(PLATFORM)/$(name_tuple)
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OUTPUT_DIR := $(firesim_base_dir)/output/$(PLATFORM)/$(name_tuple)
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# This is prefix is currently assumed by the fpga build flow
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BASE_FILE_NAME := FireSim-generated
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##########################
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# RTL Generation #
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##########################
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long_name := $(DESIGN_PACKAGE).$(DESIGN).$(TARGET_CONFIG)
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FIRRTL_FILE := $(GENERATED_DIR)/$(long_name).fir
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ANNO_FILE := $(GENERATED_DIR)/$(long_name).anno.json
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ifdef FIRESIM_STANDALONE
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firesim_sbt_project := firesim
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else
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firesim_sbt_project := {file:${firesim_base_dir}/}firesim
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endif
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chisel_src_dirs = \
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$(addprefix $(firesim_base_dir)/,. midas midas/targetutils firesim-lib) \
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$(addprefix $(chipyard_dir)/generators/, rocket-chip/src, rocket-chip/api-config-chipsalliance)
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chisel_srcs = $(foreach submodule,$(chisel_src_dirs),\
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$(shell find $(submodule)/ -iname "[!.]*.scala" -print 2> /dev/null | grep 'src/main/scala'))
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SIM_RUNTIME_CONF ?= $(GENERATED_DIR)/$(CONF_NAME)
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mem_model_args = $(shell cat $(SIM_RUNTIME_CONF))
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COMMON_SIM_ARGS ?= $(mem_model_args)
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vcs_args = +vcs+initreg+0 +vcs+initmem+0
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# Rocket Chip stage requires a fully qualified classname for each fragment, whereas Chipyard's does not.
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# This retains a consistent TARGET_CONFIG naming convention across the different target projects.
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subst_prefix=,$(TARGET_CONFIG_PACKAGE).
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$(FIRRTL_FILE) $(ANNO_FILE): $(chisel_srcs) $(FIRRTL_JAR) $(SCALA_BUILDTOOL_DEPS)
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mkdir -p $(@D)
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$(call run_scala_main,$(firesim_sbt_project),freechips.rocketchip.system.Generator, \
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--target-dir $(GENERATED_DIR) \
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--name $(long_name) \
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--top-module $(DESIGN_PACKAGE).$(DESIGN) \
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--configs $(TARGET_CONFIG_PACKAGE).$(subst _,$(subst_prefix),$(TARGET_CONFIG)))
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##########################
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# Driver Sources & Flags #
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##########################
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TESTCHIPIP_CSRC_DIR = $(chipyard_dir)/generators/testchipip/src/main/resources/testchipip/csrc
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DRIVER_DIR = $(firesim_base_dir)/src/main/cc
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FIRESIM_LIB_DIR = $(firesim_base_dir)/firesim-lib/src/main/cc/
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DRIVER_H = $(shell find $(DRIVER_DIR) -name "*.h")
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DRIVER_CC := \
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$(DRIVER_DIR)/midasexamples/simif_peek_poke.cc \
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$(DRIVER_DIR)/bridges/$(DESIGN).cc \
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$(TESTCHIPIP_CSRC_DIR)/testchip_tsi.cc \
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$(wildcard $(addprefix $(FIRESIM_LIB_DIR)/, \
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bridges/uart.cc \
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bridges/serial.cc \
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fesvr/firesim_tsi.cc \
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))
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TARGET_CXX_FLAGS := \
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-isystem $(TESTCHIPIP_CSRC_DIR) \
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-I$(DRIVER_DIR)/midasexamples \
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-I$(FIRESIM_LIB_DIR) \
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-I$(DRIVER_DIR) \
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-I$(DRIVER_DIR)/bridges \
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-g
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TARGET_LD_FLAGS := \
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-L$(RISCV)/lib \
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-lfesvr
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##########################
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# Midas-Level Sim Recipes#
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##########################
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# These are from MIDAS examples
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loadmem = $(if $(LOADMEM),+loadmem=$(abspath $(LOADMEM)),)
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benchmark = $(notdir $(basename $(if $(LOADMEM),$(notdir $(LOADMEM)),$(DESIGN))))
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logfile = $(if $(LOGFILE),$(abspath $(LOGFILE)),$(OUTPUT_DIR)/$(benchmark).$1.out)
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waveform = $(if $(WAVEFORM),$(abspath $(WAVEFORM)),$(OUTPUT_DIR)/$(benchmark).$1.$2)
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run-verilator-debug run-verilator: run-verilator% : $(GENERATED_DIR)/V$(DESIGN)% $(LOADMEM)
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mkdir -p $(OUTPUT_DIR)
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cd $(GENERATED_DIR) && ./$(notdir $<) $(COMMON_SIM_ARGS) $(ARGS) \
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$(loadmem) \
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+waveform=$(call waveform,verilator,vcd) 2> $(call logfile,verilator)
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run-vcs run-vcs-debug: run-vcs%: $(GENERATED_DIR)/$(DESIGN)% $(LOADMEM)
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mkdir -p $(OUTPUT_DIR)
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cd $(GENERATED_DIR) && ./$(notdir $<) $(vcs_args) $(COMMON_SIM_ARGS) $(ARGS) \
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$(loadmem) \
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+waveform=$(call waveform,vcs,vpd) 2> $(call logfile,vcs)
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@ -0,0 +1,30 @@
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//See LICENSE for license details.
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package firesim.bridges
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import firesim.configs.WithDefaultMemModel
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import freechips.rocketchip.config._
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import freechips.rocketchip.subsystem.{PeripheryBusKey, PeripheryBusParams}
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class NoConfig extends Config(Parameters.empty)
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class BaseBridgesConfig
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extends Config(
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new WithDefaultMemModel
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)
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class DefaultF1Config
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extends Config(
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new BaseBridgesConfig ++
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new midas.F1Config
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)
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class DefaultVitisConfig
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extends Config(
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new BaseBridgesConfig ++
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new midas.VitisConfig
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)
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class UARTConfig
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extends Config((site, here, up) => { case PeripheryBusKey =>
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PeripheryBusParams(beatBytes = 1, blockBytes = 8, dtsFrequency = Some(100000000))
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})
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|
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@ -0,0 +1,21 @@
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//See LICENSE for license details.
|
||||
|
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package firesim.bridges
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import chisel3._
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|
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import firesim.midasexamples.PeekPokeMidasExampleHarness
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import freechips.rocketchip.config.Parameters
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|
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import sifive.blocks.devices.uart.{UART, UARTParams, UARTPortIO}
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class UARTDUT(implicit val p: Parameters) extends Module {
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val uartParams = UARTParams(address = 0x10013000)
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val ep = Module(new UARTBridge(uartParams))
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ep.io.reset := reset
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ep.io.clock := clock
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ep.io.uart.txd := ep.io.uart.rxd
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}
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|
||||
class UARTModule(implicit p: Parameters) extends PeekPokeMidasExampleHarness(() => new UARTDUT)
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
//See LICENSE for license details.
|
||||
|
||||
package firesim.bridges
|
||||
|
||||
import java.io.File
|
||||
|
||||
import org.scalatest.Suites
|
||||
import org.scalatest.matchers.should._
|
||||
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.config._
|
||||
|
||||
abstract class BridgeSuite(
|
||||
val targetName: String, // See GeneratorUtils
|
||||
targetConfigs: String = "NoConfig",
|
||||
platformConfigs: String = "HostDebugFeatures_DefaultF1Config",
|
||||
tracelen: Int = 8,
|
||||
simulationArgs: Seq[String] = Seq(),
|
||||
) extends firesim.TestSuiteCommon
|
||||
with Matchers {
|
||||
|
||||
val backendSimulator = "verilator"
|
||||
|
||||
val targetTuple = s"$targetName-$targetConfigs-$platformConfigs"
|
||||
val commonMakeArgs = Seq(
|
||||
s"TARGET_PROJECT=bridges",
|
||||
s"DESIGN=$targetName",
|
||||
s"TARGET_CONFIG=${targetConfigs}",
|
||||
s"PLATFORM_CONFIG=${platformConfigs}",
|
||||
)
|
||||
|
||||
def run(
|
||||
backend: String,
|
||||
debug: Boolean = false,
|
||||
logFile: Option[File] = None,
|
||||
waveform: Option[File] = None,
|
||||
args: Seq[String] = Nil,
|
||||
) = {
|
||||
val makeArgs = Seq(
|
||||
s"run-$backend%s".format(if (debug) "-debug" else ""),
|
||||
"LOGFILE=%s".format(logFile.map(toStr).getOrElse("")),
|
||||
"WAVEFORM=%s".format(waveform.map(toStr).getOrElse("")),
|
||||
"ARGS=%s".format(args.mkString(" ")),
|
||||
)
|
||||
if (isCmdAvailable(backend)) {
|
||||
make(makeArgs: _*)
|
||||
} else 0
|
||||
}
|
||||
|
||||
/** Runs MIDAS-level simulation on the design.
|
||||
*
|
||||
* @param b
|
||||
* Backend simulator: "verilator" or "vcs"
|
||||
* @param debug
|
||||
* When true, captures waves from the simulation
|
||||
* @param args
|
||||
* A seq of PlusArgs to pass to the simulator.
|
||||
* @param shouldPass
|
||||
* When false, asserts the test returns a non-zero code
|
||||
*/
|
||||
def runTest(b: String, debug: Boolean = false, args: Seq[String] = simulationArgs, shouldPass: Boolean = true) {
|
||||
val prefix = if (shouldPass) "pass in " else "fail in "
|
||||
val testEnvStr = s"${b} MIDAS-level simulation"
|
||||
val wavesStr = if (debug) " with waves enabled" else ""
|
||||
val argStr = " with args: " + args.mkString(" ")
|
||||
|
||||
val haveThisBehavior = prefix + testEnvStr + wavesStr + argStr
|
||||
|
||||
if (isCmdAvailable(b)) {
|
||||
it should haveThisBehavior in {
|
||||
assert((run(b, debug, args = args) == 0) == shouldPass)
|
||||
}
|
||||
} else {
|
||||
ignore should haveThisBehavior in {}
|
||||
}
|
||||
}
|
||||
|
||||
mkdirs()
|
||||
behavior.of(s"$targetName")
|
||||
elaborateAndCompile()
|
||||
compileMlSimulator(backendSimulator)
|
||||
runTest(backendSimulator)
|
||||
}
|
||||
|
||||
class UARTF1Test extends BridgeSuite("UARTModule", "UARTConfig", "DefaultF1Config")
|
||||
class UARTVitisTest extends BridgeSuite("UARTModule", "UARTConfig", "DefaultVitisConfig")
|
||||
|
||||
class BridgeTests
|
||||
extends Suites(
|
||||
new UARTF1Test,
|
||||
new UARTVitisTest,
|
||||
)
|
||||
Loading…
Reference in New Issue