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[manager] Push Chisel elaboration + GG compilation to stdout (#440)

This commit is contained in:
David Biancolin 2020-04-08 19:07:47 +00:00
parent ef668479cd
commit 524f342971
1 changed files with 6 additions and 1 deletions
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7
deploy/buildtools/buildafi.py
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@ -30,7 +30,12 @@ def replace_rtl(conf, buildconfig):
rootLogger.info("Running replace-rtl to generate verilog for " + str(buildconfig.get_chisel_triplet()))
with prefix('cd ' + ddir + '/../'), prefix('source sourceme-f1-manager.sh'), prefix('export CL_DIR={}/../platforms/f1/aws-fpga/{}'.format(ddir, fpgabuilddir)), prefix('cd sim/'), StreamLogger('stdout'), StreamLogger('stderr'):
with prefix('cd ' + ddir + '/../'), \
prefix('source sourceme-f1-manager.sh'), \
prefix('export CL_DIR={}/../platforms/f1/aws-fpga/{}'.format(ddir, fpgabuilddir)), \
prefix('cd sim/'), \
InfoStreamLogger('stdout'), \
InfoStreamLogger('stderr'):
run(buildconfig.make_recipe("replace-rtl"))
run("""mkdir -p {}/results-build/{}/""".format(ddir, builddir))
run("""cp $CL_DIR/design/cl_firesim_generated.sv {}/results-build/{}/cl_firesim_generated.sv""".format(ddir, builddir))