Merge pull request #1596 from firesim/revamp-wide-tracerv-w-fix
Expand TracerV to support more than 7 IPC with FMR fix
This commit is contained in:
Abraham Gonzalez
GitHub
commit
5186829883
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@ -11,12 +11,12 @@
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# DOCREF START: Example HWDB Entry
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firesim_boom_singlecore_nic_l2_llc4mb_ddr3:
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agfi: agfi-03332c26b0bfef9cf
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agfi: agfi-0d721e90da766a06a
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deploy_quintuplet_override: null
|
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custom_runtime_config: null
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||||
# DOCREF END: Example HWDB Entry
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firesim_boom_singlecore_no_nic_l2_llc4mb_ddr3:
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agfi: agfi-0b01cb001eb3db84b
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agfi: agfi-0d851f557081a438e
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deploy_quintuplet_override: null
|
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custom_runtime_config: null
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firesim_gemmini_printf_rocket_singlecore_no_nic:
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@ -28,11 +28,11 @@ firesim_gemmini_rocket_singlecore_no_nic:
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deploy_quintuplet_override: null
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custom_runtime_config: null
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firesim_rocket_quadcore_nic_l2_llc4mb_ddr3:
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agfi: agfi-0d37db88b8d6a9ea9
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agfi: agfi-09c450553a29c35a6
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deploy_quintuplet_override: null
|
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custom_runtime_config: null
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firesim_rocket_quadcore_no_nic_l2_llc4mb_ddr3:
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agfi: agfi-05ad3a0d05b659fe8
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agfi: agfi-0f48d70c4d1f9a228
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deploy_quintuplet_override: null
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custom_runtime_config: null
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firesim_rocket_singlecore_no_nic_l2_lbp:
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@ -52,11 +52,11 @@ firesim_rocket_singlecore_sha3_no_nic_l2_llc4mb_ddr3_printf:
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deploy_quintuplet_override: null
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custom_runtime_config: null
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firesim_supernode_rocket_singlecore_nic_l2_lbp:
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agfi: agfi-0541dd890b2b59bd5
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agfi: agfi-02b5300c4b1808434
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deploy_quintuplet_override: null
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custom_runtime_config: null
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vitis_firesim_rocket_singlecore_no_nic:
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/f17bff0afb96d278c3cd199a72d9317b1bebbb2a/vitis/vitis_firesim_rocket_singlecore_no_nic.tar.gz
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/d967f09bdd1b673dba274233e5027583f3c97347/vitis/vitis_firesim_rocket_singlecore_no_nic.tar.gz
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deploy_quintuplet_override: null
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custom_runtime_config: null
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vitis_firesim_gemmini_rocket_singlecore_no_nic:
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@ -64,26 +64,26 @@ vitis_firesim_gemmini_rocket_singlecore_no_nic:
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deploy_quintuplet_override: null
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custom_runtime_config: null
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alveo_u250_firesim_rocket_singlecore_no_nic:
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/9543b082437e3ec2c3ecc863da4e06a19597e5e6/xilinx_alveo_u250/alveo_u250_firesim_rocket_singlecore_no_nic.tar.gz
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/2c884a48426bfcdcae9ed037169ee2e7d31f22e5/xilinx_alveo_u250/alveo_u250_firesim_rocket_singlecore_no_nic.tar.gz
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deploy_quintuplet_override: null
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custom_runtime_config: null
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alveo_u250_firesim_gemmini_rocket_singlecore_no_nic:
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/933a8726645fd7241f019463df86f3d117a7d714/xilinx_alveo_u250/alveo_u250_firesim_gemmini_rocket_singlecore_no_nic.tar.gz
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/3322efdde5e5ff131e39e7054c45c2c346f1c6ea/xilinx_alveo_u250/alveo_u250_firesim_gemmini_rocket_singlecore_no_nic.tar.gz
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deploy_quintuplet_override: null
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custom_runtime_config: null
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alveo_u200_firesim_rocket_singlecore_no_nic:
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/0d91a839113ab048abfed7e79fe2b0d1097f2807/xilinx_alveo_u200/alveo_u200_firesim_rocket_singlecore_no_nic.tar.gz
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/5c779585c0b2fb79a4ce2f9fdf244160077b5885/xilinx_alveo_u200/alveo_u200_firesim_rocket_singlecore_no_nic.tar.gz
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deploy_quintuplet_override: null
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custom_runtime_config: null
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alveo_u280_firesim_rocket_singlecore_no_nic:
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/a8b9ffaeb4d243292c04eb13857a7daa8ac6d897/xilinx_alveo_u280/alveo_u280_firesim_rocket_singlecore_no_nic.tar.gz
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/2e27a107fb86ea050db6dbb4afd22a4730b92974/xilinx_alveo_u280/alveo_u280_firesim_rocket_singlecore_no_nic.tar.gz
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deploy_quintuplet_override: null
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custom_runtime_config: null
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xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic:
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/48934d5a7b6b5869b446378656cf61824961471e/xilinx_vcu118/xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic.tar.gz
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/64970aad241c29d05c000b8c6516a98b37ba2517/xilinx_vcu118/xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic.tar.gz
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deploy_quintuplet_override: null
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custom_runtime_config: null
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nitefury_firesim_rocket_singlecore_no_nic:
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/f228aa51f95c3a7022444516051fd2fe346cc48d/rhsresearch_nitefury_ii/nitefury_firesim_rocket_singlecore_no_nic.tar.gz
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/2901ab775feee3565975075733a340af01db8921/rhsresearch_nitefury_ii/nitefury_firesim_rocket_singlecore_no_nic.tar.gz
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deploy_quintuplet_override: null
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custom_runtime_config: null
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@ -35,9 +35,6 @@ tracerv_t::tracerv_t(simif_t &sim,
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: streaming_bridge_driver_t(sim, stream, &KIND), mmio_addrs(mmio_addrs),
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stream_idx(stream_idx), stream_depth(stream_depth),
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max_core_ipc(max_core_ipc), clock_info(clock_info) {
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// Biancolin: move into elaboration
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assert(this->max_core_ipc <= 7 &&
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"TracerV only supports cores with a maximum IPC <= 7");
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const char *tracefilename = nullptr;
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const char *dwarf_file_name = nullptr;
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this->tracefile = nullptr;
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@ -272,8 +269,6 @@ void tracerv_t::serialize(
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OUTBUF[i + 0],
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q,
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OUTBUF[i + q + 1] & (~valid_mask));
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} else {
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break;
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}
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}
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}
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@ -5,7 +5,6 @@
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#include "core/bridge_driver.h"
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#include "core/clock_info.h"
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#include <functional>
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#include <iostream>
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#include <vector>
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class TraceTracker;
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@ -14,20 +14,19 @@ import midas.widgets._
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class TracerVTargetIO(widths: TraceBundleWidths) extends Bundle {
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val trace = Input(new SerializableTileTraceIO(widths))
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val triggerCredit = Output(Bool())
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val triggerDebit = Output(Bool())
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val triggerDebit = Output(Bool())
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}
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/**
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* Target-side module for the TracerV Bridge.
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/** Target-side module for the TracerV Bridge.
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*
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* @param insnWidths A case class containing the widths of configurable-length
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* fields in the trace interface.
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* @param insnWidths
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* A case class containing the widths of configurable-length fields in the trace interface.
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*
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* @param numInsns The number of instructions captured in a single a cycle
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* (generally, the commit width of the pipeline)
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* @param numInsns
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* The number of instructions captured in a single a cycle (generally, the commit width of the pipeline)
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*
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* Warning: If you're not going to use the companion object to instantiate
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* this bridge you must call [[TracerVBridge.generateTriggerAnnotations] _in
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* the parent module_.
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* Warning: If you're not going to use the companion object to instantiate this bridge you must call
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* [[TracerVBridge.generateTriggerAnnotations] _in the parent module_.
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*/
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class TracerVBridge(widths: TraceBundleWidths)
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extends BlackBox
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@ -66,7 +65,7 @@ object TracerVBridge {
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tracerv
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}
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def apply(tracedInsns: TileTraceIO)(implicit p:Parameters): TracerVBridge = {
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def apply(tracedInsns: TileTraceIO)(implicit p: Parameters): TracerVBridge = {
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val tracerv = withClockAndReset(tracedInsns.clock, tracedInsns.reset) {
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TracerVBridge(tracedInsns.traceBundleWidths)
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}
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@ -87,75 +86,75 @@ class TracerVBridgeModule(key: TraceBundleWidths)(implicit p: Parameters)
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val io = IO(new WidgetIO)
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val hPort = IO(HostPort(new TracerVTargetIO(key)))
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// Mask off valid committed instructions when under reset
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val traces = hPort.hBits.trace.trace.insns.map({ unmasked =>
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val masked = WireDefault(unmasked)
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masked.valid := unmasked.valid && !hPort.hBits.trace.reset.asBool
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masked
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})
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private val pcWidth = traces.map(_.iaddr.getWidth).max
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private val pcWidth = traces.map(_.iaddr.getWidth).max
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private val insnWidth = traces.map(_.insn.getWidth).max
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val cycleCountWidth = 64
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val cycleCountWidth = 64
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// Set after trigger-dependent memory-mapped registers have been set, to
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// prevent spurious credits
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val initDone = genWORegInit(Wire(Bool()), "initDone", false.B)
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val initDone = genWORegInit(Wire(Bool()), "initDone", false.B)
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// When unset, diables token capture to improve FMR, while still enabling the
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// use of TracerV-based triggers
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val traceEnable = genWORegInit(Wire(Bool()), "traceEnable", true.B)
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val traceEnable = genWORegInit(Wire(Bool()), "traceEnable", true.B)
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//Program Counter trigger value can be configured externally
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val hostTriggerPCWidthOffset = pcWidth - p(CtrlNastiKey).dataBits
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val hostTriggerPCLowWidth = if (hostTriggerPCWidthOffset > 0) p(CtrlNastiKey).dataBits else pcWidth
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val hostTriggerPCHighWidth = if (hostTriggerPCWidthOffset > 0) hostTriggerPCWidthOffset else 0
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val hostTriggerPCLowWidth = if (hostTriggerPCWidthOffset > 0) p(CtrlNastiKey).dataBits else pcWidth
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val hostTriggerPCHighWidth = if (hostTriggerPCWidthOffset > 0) hostTriggerPCWidthOffset else 0
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val hostTriggerPCStartHigh = RegInit(0.U(hostTriggerPCHighWidth.W))
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val hostTriggerPCStartLow = RegInit(0.U(hostTriggerPCLowWidth.W))
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val hostTriggerPCStartLow = RegInit(0.U(hostTriggerPCLowWidth.W))
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attach(hostTriggerPCStartHigh, "hostTriggerPCStartHigh", WriteOnly)
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attach(hostTriggerPCStartLow, "hostTriggerPCStartLow", WriteOnly)
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val hostTriggerPCStart = Cat(hostTriggerPCStartHigh, hostTriggerPCStartLow)
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val triggerPCStart = RegInit(0.U(pcWidth.W))
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val hostTriggerPCStart = Cat(hostTriggerPCStartHigh, hostTriggerPCStartLow)
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val triggerPCStart = RegInit(0.U(pcWidth.W))
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triggerPCStart := hostTriggerPCStart
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val hostTriggerPCEndHigh = RegInit(0.U(hostTriggerPCHighWidth.W))
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val hostTriggerPCEndLow = RegInit(0.U(hostTriggerPCLowWidth.W))
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val hostTriggerPCEndLow = RegInit(0.U(hostTriggerPCLowWidth.W))
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attach(hostTriggerPCEndHigh, "hostTriggerPCEndHigh", WriteOnly)
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attach(hostTriggerPCEndLow, "hostTriggerPCEndLow", WriteOnly)
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val hostTriggerPCEnd = Cat(hostTriggerPCEndHigh, hostTriggerPCEndLow)
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val triggerPCEnd = RegInit(0.U(pcWidth.W))
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val hostTriggerPCEnd = Cat(hostTriggerPCEndHigh, hostTriggerPCEndLow)
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val triggerPCEnd = RegInit(0.U(pcWidth.W))
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triggerPCEnd := hostTriggerPCEnd
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//Cycle count trigger
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val hostTriggerCycleCountWidthOffset = 64 - p(CtrlNastiKey).dataBits
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val hostTriggerCycleCountLowWidth = if (hostTriggerCycleCountWidthOffset > 0) p(CtrlNastiKey).dataBits else 64
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val hostTriggerCycleCountHighWidth = if (hostTriggerCycleCountWidthOffset > 0) hostTriggerCycleCountWidthOffset else 0
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val hostTriggerCycleCountLowWidth = if (hostTriggerCycleCountWidthOffset > 0) p(CtrlNastiKey).dataBits else 64
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val hostTriggerCycleCountHighWidth =
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if (hostTriggerCycleCountWidthOffset > 0) hostTriggerCycleCountWidthOffset else 0
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val hostTriggerCycleCountStartHigh = RegInit(0.U(hostTriggerCycleCountHighWidth.W))
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val hostTriggerCycleCountStartLow = RegInit(0.U(hostTriggerCycleCountLowWidth.W))
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val hostTriggerCycleCountStartLow = RegInit(0.U(hostTriggerCycleCountLowWidth.W))
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attach(hostTriggerCycleCountStartHigh, "hostTriggerCycleCountStartHigh", WriteOnly)
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attach(hostTriggerCycleCountStartLow, "hostTriggerCycleCountStartLow", WriteOnly)
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val hostTriggerCycleCountStart = Cat(hostTriggerCycleCountStartHigh, hostTriggerCycleCountStartLow)
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val triggerCycleCountStart = RegInit(0.U(cycleCountWidth.W))
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val hostTriggerCycleCountStart = Cat(hostTriggerCycleCountStartHigh, hostTriggerCycleCountStartLow)
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val triggerCycleCountStart = RegInit(0.U(cycleCountWidth.W))
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triggerCycleCountStart := hostTriggerCycleCountStart
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val hostTriggerCycleCountEndHigh = RegInit(0.U(hostTriggerCycleCountHighWidth.W))
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val hostTriggerCycleCountEndLow = RegInit(0.U(hostTriggerCycleCountLowWidth.W))
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val hostTriggerCycleCountEndLow = RegInit(0.U(hostTriggerCycleCountLowWidth.W))
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attach(hostTriggerCycleCountEndHigh, "hostTriggerCycleCountEndHigh", WriteOnly)
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attach(hostTriggerCycleCountEndLow, "hostTriggerCycleCountEndLow", WriteOnly)
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val hostTriggerCycleCountEnd = Cat(hostTriggerCycleCountEndHigh, hostTriggerCycleCountEndLow)
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val triggerCycleCountEnd = RegInit(0.U(cycleCountWidth.W))
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val hostTriggerCycleCountEnd = Cat(hostTriggerCycleCountEndHigh, hostTriggerCycleCountEndLow)
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val triggerCycleCountEnd = RegInit(0.U(cycleCountWidth.W))
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triggerCycleCountEnd := hostTriggerCycleCountEnd
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val trace_cycle_counter = RegInit(0.U(cycleCountWidth.W))
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//target instruction type trigger (trigger through target software)
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//can configure the trigger instruction type externally though simulation driver
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val hostTriggerStartInst = RegInit(0.U(insnWidth.W))
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val hostTriggerStartInst = RegInit(0.U(insnWidth.W))
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val hostTriggerStartInstMask = RegInit(0.U(insnWidth.W))
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attach(hostTriggerStartInst, "hostTriggerStartInst", WriteOnly)
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attach(hostTriggerStartInstMask, "hostTriggerStartInstMask", WriteOnly)
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val hostTriggerEndInst = RegInit(0.U(insnWidth.W))
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val hostTriggerEndInst = RegInit(0.U(insnWidth.W))
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val hostTriggerEndInstMask = RegInit(0.U(insnWidth.W))
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attach(hostTriggerEndInst, "hostTriggerEndInst", WriteOnly)
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attach(hostTriggerEndInstMask, "hostTriggerEndInstMask", WriteOnly)
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@ -171,10 +170,10 @@ class TracerVBridgeModule(key: TraceBundleWidths)(implicit p: Parameters)
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val triggerPCValVec = RegInit(VecInit(Seq.fill(traces.length)(false.B)))
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traces.zipWithIndex.foreach { case (trace, i) =>
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when (trace.valid) {
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when (triggerPCStart === trace.iaddr) {
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when(trace.valid) {
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when(triggerPCStart === trace.iaddr) {
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triggerPCValVec(i) := true.B
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} .elsewhen ((triggerPCEnd === trace.iaddr) && triggerPCValVec(i)) {
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}.elsewhen((triggerPCEnd === trace.iaddr) && triggerPCValVec(i)) {
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triggerPCValVec(i) := false.B
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}
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}
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@ -182,36 +181,86 @@ class TracerVBridgeModule(key: TraceBundleWidths)(implicit p: Parameters)
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val triggerInstValVec = RegInit(VecInit(Seq.fill(traces.length)(false.B)))
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traces.zipWithIndex.foreach { case (trace, i) =>
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when (trace.valid) {
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when (!((hostTriggerStartInst ^ trace.insn) & hostTriggerStartInstMask).orR) {
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when(trace.valid) {
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when(!((hostTriggerStartInst ^ trace.insn) & hostTriggerStartInstMask).orR) {
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triggerInstValVec(i) := true.B
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} .elsewhen (!((hostTriggerEndInst ^ trace.insn) & hostTriggerEndInstMask).orR) {
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}.elsewhen(!((hostTriggerEndInst ^ trace.insn) & hostTriggerEndInstMask).orR) {
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triggerInstValVec(i) := false.B
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}
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}
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}
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val trigger = MuxLookup(triggerSelector, false.B, Seq(
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0.U -> true.B,
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1.U -> triggerCycleCountVal,
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2.U -> triggerPCValVec.reduce(_ || _),
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3.U -> triggerInstValVec.reduce(_ || _)))
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val trigger = MuxLookup(
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triggerSelector,
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false.B,
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Seq(
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0.U -> true.B,
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1.U -> triggerCycleCountVal,
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2.U -> triggerPCValVec.reduce(_ || _),
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3.U -> triggerInstValVec.reduce(_ || _),
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),
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)
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val tFireHelper = DecoupledHelper(streamEnq.ready, hPort.toHost.hValid, hPort.fromHost.hReady, initDone)
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// the maximum width of a single arm, this is determined by the 512 bit width of a single beat
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val armWidth = 7
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val triggerReg = RegEnable(trigger, false.B, tFireHelper.fire())
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hPort.hBits.triggerDebit := !trigger && triggerReg
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// divide with a ceiling round, to get the total number of arms
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val armCount = (traces.length + armWidth - 1) / armWidth
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// A Seq of Seq which represents each arm of the mux
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val allTraceArms = traces.grouped(armWidth).toSeq
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// an intermediate value used to build allStreamBits
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val allUintTraces = allTraceArms.map(arm => arm.map((trace => Cat(trace.valid, trace.iaddr).pad(64))).reverse)
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// Literally each arm of the mux, these are directly the bits that get put into the bump
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val allStreamBits =
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allUintTraces.map(uarm => Cat(uarm :+ trace_cycle_counter.pad(64)).pad(BridgeStreamConstants.streamWidthBits))
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||||
|
||||
// Number of bits to use for the counter, the +1 is required because the counter will count 1 past the number of arms
|
||||
val counterBits = log2Ceil(armCount + 1)
|
||||
|
||||
// This counter acts to select the mux arm
|
||||
val counter = RegInit(0.U(counterBits.W))
|
||||
|
||||
// The main mux where the input arms are different possible valid traces, and the output goes to streamEnq
|
||||
val streamMux = MuxLookup(counter, allStreamBits(0), Seq.tabulate(armCount)(x => x.U -> allStreamBits(x)))
|
||||
|
||||
// a parallel set of arms to a parallel mux, true if any instructions in the arm are valid (OR reduction)
|
||||
val anyValid = allTraceArms.map(arm => arm.map(trace => trace.valid).reduce((a, b) => (a | b)))
|
||||
|
||||
// all of the valids of the larger indexed arms are OR reduced
|
||||
val anyValidRemain =
|
||||
Seq.tabulate(armCount)(idx => (idx until armCount).map(x => anyValid(x)).reduce((a, b) => (a | b)))
|
||||
val anyValidRemainMux = MuxLookup(counter, false.B, Seq.tabulate(armCount)(x => x.U -> anyValidRemain(x)))
|
||||
|
||||
streamEnq.bits := streamMux
|
||||
|
||||
val maybeFire = !anyValidRemainMux || (counter === (armCount - 1).U)
|
||||
val maybeEnq = anyValidRemainMux
|
||||
|
||||
val commonPredicates = Seq(hPort.toHost.hValid, hPort.fromHost.hReady, streamEnq.ready, initDone)
|
||||
val do_enq_helper = DecoupledHelper((Seq(maybeEnq, traceEnable) ++ commonPredicates):_*)
|
||||
val do_fire_helper = DecoupledHelper((maybeFire +: commonPredicates):_*)
|
||||
|
||||
// Note, if we dequeue a token that wins out over the increment below
|
||||
when(do_fire_helper.fire()) {
|
||||
counter := 0.U
|
||||
}.elsewhen(do_enq_helper.fire()) {
|
||||
counter := counter + 1.U
|
||||
}
|
||||
|
||||
streamEnq.valid := do_enq_helper.fire(streamEnq.ready, trigger)
|
||||
hPort.toHost.hReady := do_fire_helper.fire(hPort.toHost.hValid)
|
||||
|
||||
// Output token (back to hub model) handling.
|
||||
val triggerReg = RegEnable(trigger, false.B, do_fire_helper.fire())
|
||||
hPort.hBits.triggerDebit := !trigger && triggerReg
|
||||
hPort.hBits.triggerCredit := trigger && !triggerReg
|
||||
|
||||
val uint_traces = (traces map (trace => Cat(trace.valid, trace.iaddr).pad(64))).reverse
|
||||
streamEnq.bits := Cat(uint_traces :+ trace_cycle_counter.pad(64)).pad(BridgeStreamConstants.streamWidthBits)
|
||||
hPort.fromHost.hValid := do_fire_helper.fire(hPort.fromHost.hReady)
|
||||
|
||||
hPort.toHost.hReady := tFireHelper.fire(hPort.toHost.hValid)
|
||||
hPort.fromHost.hValid := tFireHelper.fire(hPort.fromHost.hReady)
|
||||
|
||||
streamEnq.valid := tFireHelper.fire(streamEnq.ready, trigger) && traceEnable
|
||||
|
||||
when (tFireHelper.fire()) {
|
||||
when(hPort.toHost.fire) {
|
||||
trace_cycle_counter := trace_cycle_counter + 1.U
|
||||
}
|
||||
|
||||
|
|
@ -219,17 +268,17 @@ class TracerVBridgeModule(key: TraceBundleWidths)(implicit p: Parameters)
|
|||
|
||||
override def genHeader(base: BigInt, memoryRegions: Map[String, BigInt], sb: StringBuilder): Unit = {
|
||||
genConstructor(
|
||||
base,
|
||||
sb,
|
||||
"tracerv_t",
|
||||
"tracerv",
|
||||
Seq(
|
||||
UInt32(toHostStreamIdx),
|
||||
UInt32(toHostCPUQueueDepth),
|
||||
UInt32(traces.size),
|
||||
Verbatim(clockDomainInfo.toC)
|
||||
),
|
||||
hasStreams = true
|
||||
base,
|
||||
sb,
|
||||
"tracerv_t",
|
||||
"tracerv",
|
||||
Seq(
|
||||
UInt32(toHostStreamIdx),
|
||||
UInt32(toHostCPUQueueDepth),
|
||||
UInt32(traces.size),
|
||||
Verbatim(clockDomainInfo.toC),
|
||||
),
|
||||
hasStreams = true,
|
||||
)
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -10,10 +10,12 @@
|
|||
#include <iostream>
|
||||
#include <string_view>
|
||||
|
||||
static std::vector<bool> get_contiguous(unsigned bits, unsigned total) {
|
||||
static std::vector<bool> get_valids(uint64_t seed, unsigned total) {
|
||||
assert(total <= 64 && "This test does not support more than 64 IPC");
|
||||
|
||||
std::vector<bool> ret;
|
||||
for (unsigned i = 0; i < total; i++) {
|
||||
const bool value = (i < bits);
|
||||
const bool value = seed & (1 << i);
|
||||
ret.emplace_back(value);
|
||||
}
|
||||
|
||||
|
|
@ -168,12 +170,16 @@ public:
|
|||
// calculate what TraverV should output, and save it
|
||||
if (bit[i]) {
|
||||
valid_i.emplace_back(iad[i]);
|
||||
} else {
|
||||
// write a magic value to signify an invalid instruction
|
||||
// this magic value is test only and is not passed to the DUT
|
||||
valid_i.emplace_back(-1);
|
||||
}
|
||||
}
|
||||
|
||||
// place instructions onto the vector 7 at a time
|
||||
for (size_t i = 0; i < valid_i.size(); i += 7) {
|
||||
auto last = std::min(valid_i.size(), i + 7);
|
||||
const auto last = std::min(valid_i.size(), i + 7);
|
||||
std::vector<uint64_t> chunk =
|
||||
std::vector<uint64_t>(valid_i.begin() + i, valid_i.begin() + last);
|
||||
expected_pair.emplace_back(std::make_pair(e_cycle, chunk));
|
||||
|
|
@ -187,10 +193,10 @@ public:
|
|||
for (unsigned test_step = 0, total = get_total_trace_tests();
|
||||
test_step < total;
|
||||
++test_step) {
|
||||
const uint64_t pull = rand_next(tracerv_width + 1);
|
||||
const uint64_t pull = rand_next();
|
||||
|
||||
auto pull_iaddr = get_iaddrs(test_step, tracerv_width);
|
||||
auto pull_bits = get_contiguous(pull, tracerv_width);
|
||||
const auto pull_bits = get_valids(pull, tracerv_width);
|
||||
const auto pull_iaddr = get_iaddrs(test_step, tracerv_width);
|
||||
|
||||
load(pull_iaddr, pull_bits);
|
||||
steps(1);
|
||||
|
|
@ -310,7 +316,12 @@ public:
|
|||
assert(insns.size() < 8 && "Internal test error, filtered cannot "
|
||||
"have more than 8 instructions at once");
|
||||
for (int i = 0; i < insns.size(); i++) {
|
||||
buffer[i + 1] = insns[i] | tracerv_t::valid_mask;
|
||||
// valid instruction, or invalid placeholder
|
||||
if (insns[i] != -1) {
|
||||
buffer[i + 1] = insns[i] | tracerv_t::valid_mask;
|
||||
} else {
|
||||
buffer[i + 1] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
// because filtered doesn't contain the instruction value for non
|
||||
|
|
@ -339,7 +350,7 @@ public:
|
|||
/**
|
||||
* Returns the next available random number, modulo limit.
|
||||
*/
|
||||
uint64_t rand_next(uint64_t limit) { return gen() % limit; }
|
||||
uint64_t rand_next() { return gen(); }
|
||||
|
||||
private:
|
||||
unsigned get_total_trace_tests() const { return 128; }
|
||||
|
|
|
|||
|
|
@ -34,6 +34,11 @@ class TracerVModuleTestCount7
|
|||
7
|
||||
})
|
||||
|
||||
class TracerVModuleTestCount9
|
||||
extends Config((site, here, up) => { case TracerVModuleInstructionCount =>
|
||||
9
|
||||
})
|
||||
|
||||
class TracerVModuleTestCount14
|
||||
extends Config((site, here, up) => { case TracerVModuleInstructionCount =>
|
||||
14
|
||||
|
|
|
|||
|
|
@ -56,9 +56,12 @@ abstract class TracerVTestBase(
|
|||
}
|
||||
}
|
||||
|
||||
class TracerVF1TestCount1 extends TracerVTestBase(BaseConfigs.F1, 1);
|
||||
class TracerVF1TestCount1 extends TracerVTestBase(BaseConfigs.F1, 1);
|
||||
// This test is disabled until FireSim issue #1428 is resolved
|
||||
// class TracerVF1TestCount5 extends TracerVTestBase(BaseConfigs.F1, 5, Some(3), Some("FF0000001C")); // in hex
|
||||
class TracerVF1TestCount6 extends TracerVTestBase(BaseConfigs.F1, 6, Some(2), Some("3000")); // in hex
|
||||
class TracerVF1TestCount7 extends TracerVTestBase(BaseConfigs.F1, 7, Some(1), Some("9")); // in decimala
|
||||
class TracerVVitisTest extends TracerVTestBase(BaseConfigs.Vitis, 7);
|
||||
class TracerVF1TestCount6 extends TracerVTestBase(BaseConfigs.F1, 6, Some(2), Some("3000")); // in hex
|
||||
class TracerVF1TestCount7 extends TracerVTestBase(BaseConfigs.F1, 7, Some(1), Some("9")); // in decimal
|
||||
class TracerVF1TestCount9 extends TracerVTestBase(BaseConfigs.F1, 9);
|
||||
class TracerVVitisTest extends TracerVTestBase(BaseConfigs.Vitis, 14);
|
||||
class TracerVF1TestCount14 extends TracerVTestBase(BaseConfigs.F1, 14, Some(1), Some("10")); // in decimal
|
||||
class TracerVF1TestCount15 extends TracerVTestBase(BaseConfigs.F1, 15, Some(2), Some("4000"));
|
||||
|
|
|
|||
Loading…
Reference in New Issue