replica
/
firesim
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

reading output

This commit is contained in:
Sagar Karandikar 2020-02-09 00:59:05 +00:00
parent 87144e2a4f
commit 507b6f72e6
2 changed files with 72 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
docs/Advanced-Usage/Debugging-and-Profiling-on-FPGA/TRACERV-HUMAN-READABLE-EXAMPLE Normal file
View File

@ -0,0 +1,30 @@
C0: 0000010000010040, cycle: 0000000000000046
C0: 0000010000010044, cycle: 0000000000000047
C0: 0000010000010048, cycle: 0000000000000048
C0: 000001000001004c, cycle: 000000000000004d
C0: 0000010000010050, cycle: 000000000000004e
C0: 0000010000010054, cycle: 0000000000000053
C0: 0000010000010058, cycle: 0000000000000058
C0: 000001000001005c, cycle: 000000000000005d
C0: 0000010000010060, cycle: 00000000003d2e94
C0: 0000010000010000, cycle: 00000000003d2ea7
C0: 0000010000010004, cycle: 00000000003d2ea8
C0: 0000010000010008, cycle: 00000000003d2eab
C0: 000001000001000c, cycle: 00000000003d2eac
C0: 0000010000010064, cycle: 00000000003d2ead
C0: 0000010000010068, cycle: 00000000003d2eb5
C0: 0000010000010064, cycle: 00000000003d2eb9
C0: 0000010000010068, cycle: 00000000003d2ec9
C0: 000001000001006c, cycle: 00000000003d2eca
C0: 0000010000010070, cycle: 00000000003d2ecb
C0: 0000010000010074, cycle: 00000000003d2ecc
C0: 0000010000010078, cycle: 00000000003d2ecd
C0: 000001000001007c, cycle: 00000000003d2ece
C0: 0000010000010080, cycle: 00000000003d2ee6
C0: 0000010000010084, cycle: 00000000003d2ee7
C0: 0000010000010088, cycle: 00000000003d2ee8
C0: 000001000001008c, cycle: 00000000003d2ee9
C0: 0000010000010090, cycle: 00000000003d2eea
C0: 0000010000010094, cycle: 00000000003d2eeb
C0: 0000010000010098, cycle: 00000000003d2ef0
C0: 0000010080000000, cycle: 00000000003d2f23

42
docs/Advanced-Usage/Debugging-and-Profiling-on-FPGA/TracerV.rst
View File

@ -124,6 +124,48 @@ The four triggering methods available in FireSim are as follows:
Interpreting the Trace Result
------------------------------
Human readable output
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This is ``output_format=0``.
The human readable trace output format looks like so:
.. include:: TRACERV-HUMAN-READABLE-EXAMPLE
:code: ini
In this output, C0 represents instruction stream (or core) zero. The next field
represents the address of the instruction committed that cycle and a valid bit,
in hex, interpreted like so:
.. code-block::
0000010080000000
^|--------|
| \--- 40 bits of address
|
\-------- valid bit
The final field is the target cycle on which this instruction was committed,
in hex.
Binary output
^^^^^^^^^^^^^^^^^
This is ``output_format=1``.
This simply writes the 512 bits received from the FPGA each cycle to the output
file in binary. Each 512-bit chunk is stored little-endian, that is, the first
64-bits stores the address and valid bits of core 0 in little-endian, the next
64-bits stores the address and valid bits of core 1 in little-endian, and so on,
until the final 64-bit value in the 512-bit value, which stores the cycle number
in little-endian.
Flame Graph output
^^^^^^^^^^^^^^^^^^^^
This is ``output_format=2``. See the :ref:`tracerv-with-flamegraphs` section.
Caveats
--------------------