FPGATop: Ensure insertion order = iteration order on WidgetMap
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@ -12,6 +12,7 @@ import freechips.rocketchip.config.{Parameters, Field}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util.{DecoupledHelper, HeterogeneousBag}
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import freechips.rocketchip.util.{DecoupledHelper, HeterogeneousBag}
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import scala.collection.immutable.ListMap
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import scala.collection.mutable
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import scala.collection.mutable
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/**
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/**
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@ -76,7 +77,8 @@ class FPGATop(implicit p: Parameters) extends LazyModule with UnpackedWrapperCon
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"Simulation control bus must be 32-bits wide per AXI4-lite specification")
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"Simulation control bus must be 32-bits wide per AXI4-lite specification")
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lazy val config = p(SimWrapperKey)
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lazy val config = p(SimWrapperKey)
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val master = addWidget(new SimulationMaster)
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val master = addWidget(new SimulationMaster)
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val bridgeModuleMap: Map[BridgeIOAnnotation, BridgeModule[_ <: Record with HasChannels]] = bridgeAnnos.map(anno => anno -> addWidget(anno.elaborateWidget)).toMap
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val bridgeModuleMap: ListMap[BridgeIOAnnotation, BridgeModule[_ <: Record with HasChannels]] =
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ListMap((bridgeAnnos.map(anno => anno -> addWidget(anno.elaborateWidget))):_*)
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// Find all bridges that wish to be allocated FPGA DRAM, and group them
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// Find all bridges that wish to be allocated FPGA DRAM, and group them
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// according to their memoryRegionName. Requested addresses will be unified
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// according to their memoryRegionName. Requested addresses will be unified
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