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FPGATop: Ensure insertion order = iteration order on WidgetMap

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David Biancolin 2022-04-13 17:02:09 +00:00 committed by Cloud User
parent 433ccf4c96
commit 50151c12d4
1 changed files with 3 additions and 1 deletions
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4
sim/midas/src/main/scala/midas/core/FPGATop.scala
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@ -12,6 +12,7 @@ import freechips.rocketchip.config.{Parameters, Field}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util.{DecoupledHelper, HeterogeneousBag}
import scala.collection.immutable.ListMap
import scala.collection.mutable
/**
@ -76,7 +77,8 @@ class FPGATop(implicit p: Parameters) extends LazyModule with UnpackedWrapperCon
"Simulation control bus must be 32-bits wide per AXI4-lite specification")
lazy val config = p(SimWrapperKey)
val master = addWidget(new SimulationMaster)
val bridgeModuleMap: Map[BridgeIOAnnotation, BridgeModule[_ <: Record with HasChannels]] = bridgeAnnos.map(anno => anno -> addWidget(anno.elaborateWidget)).toMap
val bridgeModuleMap: ListMap[BridgeIOAnnotation, BridgeModule[_ <: Record with HasChannels]] =
ListMap((bridgeAnnos.map(anno => anno -> addWidget(anno.elaborateWidget))):_*)
// Find all bridges that wish to be allocated FPGA DRAM, and group them
// according to their memoryRegionName. Requested addresses will be unified