Merge remote-tracking branch 'origin/main' into faster-conda-lock
This commit is contained in:
abejgonzalez
commit
47bac3422c
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@ -2,7 +2,7 @@
|
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|
||||
This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/
|
||||
|
||||
## [1.17.1] - 2023-07-12
|
||||
## [1.17.1] - 2023-07-14
|
||||
Fix missing mcs file in VCU118 bitstream_tar. Automatically generate release notes for faster releases. CI improvements.
|
||||
|
||||
### Added
|
||||
|
|
@ -15,6 +15,7 @@ Fix missing mcs file in VCU118 bitstream_tar. Automatically generate release not
|
|||
|
||||
### Fixed
|
||||
- Fix VCU118 bitstream_tar missing mcs file (by @abejgonzalez in https://github.com/firesim/firesim/pull/1592)
|
||||
- Additional VCU118 initial setup fixes (by @sagark in https://github.com/firesim/firesim/pull/1606)
|
||||
|
||||
**Full Changelog:** https://github.com/firesim/firesim/compare/1.17.0...main
|
||||
|
||||
|
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|
|||
|
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@ -685,6 +685,7 @@ class XilinxAlveoBitBuilder(BitBuilder):
|
|||
local_cl_dir = f"{local_results_dir}/{fpga_build_postfix}"
|
||||
bit_path = f"{local_cl_dir}/vivado_proj/firesim.bit"
|
||||
mcs_path = f"{local_cl_dir}/vivado_proj/firesim.mcs"
|
||||
mcs_secondary_path = f"{local_cl_dir}/vivado_proj/firesim_secondary.mcs"
|
||||
tar_staging_path = f"{local_cl_dir}/{self.build_config.PLATFORM}"
|
||||
tar_name = "firesim.tar.gz"
|
||||
|
||||
|
|
@ -695,6 +696,8 @@ class XilinxAlveoBitBuilder(BitBuilder):
|
|||
# store bitfile (and mcs if it exists)
|
||||
local(f"cp {bit_path} {tar_staging_path}")
|
||||
local(f"cp {mcs_path} {tar_staging_path}")
|
||||
if self.build_config.PLATFORM == "xilinx_vcu118":
|
||||
local(f"cp {mcs_secondary_path} {tar_staging_path}")
|
||||
|
||||
# store metadata string
|
||||
local(f"""echo '{self.get_metadata_string()}' >> {tar_staging_path}/metadata""")
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ firesim_supernode_rocket_singlecore_nic_l2_lbp:
|
|||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
vitis_firesim_rocket_singlecore_no_nic:
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/23fc86bcade868b892f245a1d93de985e7ea10a8/vitis/vitis_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/9697ea5f5f297e386c5c6f60ba5a71ee3020f93f/vitis/vitis_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
vitis_firesim_gemmini_rocket_singlecore_no_nic:
|
||||
|
|
@ -64,26 +64,26 @@ vitis_firesim_gemmini_rocket_singlecore_no_nic:
|
|||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
alveo_u250_firesim_rocket_singlecore_no_nic:
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/e0fbdb133ace9ee73121fd2b5ac4ac6ebcd681e0/xilinx_alveo_u250/alveo_u250_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/ac2cd0c123e1755a666d48709021d29abb440ab6/xilinx_alveo_u250/alveo_u250_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
alveo_u250_firesim_gemmini_rocket_singlecore_no_nic:
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/709b988e36201250a60cdb46b66483565cc9a701/xilinx_alveo_u250/alveo_u250_firesim_gemmini_rocket_singlecore_no_nic.tar.gz
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/ebeffff3cd54225fbbcac36a8f2ced5645f2079e/xilinx_alveo_u250/alveo_u250_firesim_gemmini_rocket_singlecore_no_nic.tar.gz
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
alveo_u200_firesim_rocket_singlecore_no_nic:
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/48c880eb7afc103733e0ea766f8413a5856c3771/xilinx_alveo_u200/alveo_u200_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/9fa5d271407bd7057885c02f19f510842f3f3c95/xilinx_alveo_u200/alveo_u200_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
alveo_u280_firesim_rocket_singlecore_no_nic:
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/11ce62962fe3f6ddc52c3cd76e03dec111206f42/xilinx_alveo_u280/alveo_u280_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/808bce6788100b700730bd5b39b86e5c004cf43d/xilinx_alveo_u280/alveo_u280_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic:
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/41aa6a93316788aadd05f557b2f2b43417ba6702/xilinx_vcu118/xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic.tar.gz
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/c3adc1471a61cb1415a0c800271baad5bf753d02/xilinx_vcu118/xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic.tar.gz
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
nitefury_firesim_rocket_singlecore_no_nic:
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/66257f4896490cf5c2621ac77b9bf1301708b9e0/rhsresearch_nitefury_ii/nitefury_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/7fa19e457374d98cc7abf7a196b93db23db2dc52/rhsresearch_nitefury_ii/nitefury_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
|
|
@ -413,7 +413,7 @@ Specifies the host FPGA frequency for a bitstream build.
|
|||
|
||||
Specifies a pre-canned set of strategies and directives to pass to the
|
||||
bitstream build. Note, these are implemented differently on different host
|
||||
platforms, but try to optimize for the same things. Strategies supported across both Vitis, Xilinx Alveo U250/U280, and EC2 F1 include:
|
||||
platforms, but try to optimize for the same things. Strategies supported across both Vitis, Xilinx Alveo U200/U250/U280, and EC2 F1 include:
|
||||
|
||||
- ``TIMING``: Optimize for improved fmax.
|
||||
- ``AREA``: Optimize for reduced resource utilization.
|
||||
|
|
@ -748,7 +748,7 @@ simulations across all run farm hosts.
|
|||
For example, this class manages how to flash FPGAs with bitstreams, how to copy back results, and how to check if a simulation is running.
|
||||
By default, deploy platform classes can be found in :gh-file-ref:`deploy/runtools/run_farm_deploy_managers.py`. However, you can specify
|
||||
your own custom run farm classes by adding your python file to the ``PYTHONPATH``.
|
||||
There are default deploy managers / platforms that correspond to AWS EC2 F1 FPGAs, Vitis FPGAs, Xilinx Alveo U250/U280 FPGAs, Xilinx VCU118 FPGAs, and RHS Research Nitefury II FPGAs: ``EC2InstanceDeployManager``, ``VitisInstanceDeployManager``, ``Xilinx{AlveoU250,AlveoU280,VCU118}InstanceDeployManager``, and ``RHSResearchNitefuryIIInstanceDeployManager`` respectively.
|
||||
There are default deploy managers / platforms that correspond to AWS EC2 F1 FPGAs, Vitis FPGAs, Xilinx Alveo U200/U250/U280 FPGAs, Xilinx VCU118 FPGAs, and RHS Research Nitefury II FPGAs: ``EC2InstanceDeployManager``, ``VitisInstanceDeployManager``, ``Xilinx{AlveoU200,AlveoU250,AlveoU280,VCU118}InstanceDeployManager``, and ``RHSResearchNitefuryIIInstanceDeployManager`` respectively.
|
||||
For example, to use the ``EC2InstanceDeployManager`` deploy platform class, you would write ``default_platform: EC2InstanceDeployManager``.
|
||||
|
||||
``default_simulation_dir``
|
||||
|
|
@ -948,6 +948,11 @@ Here is an example of this configuration file:
|
|||
.. literalinclude:: /../deploy/bit-builder-recipes/vitis.yaml
|
||||
:language: yaml
|
||||
|
||||
``xilinx_alveo_u200.yaml`` bit builder recipe
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
This bit builder recipe configures a build farm host to build an Xilinx Alveo U200 bitstream, packaged into a ``bitstream_tar``.
|
||||
|
||||
``xilinx_alveo_u250.yaml`` bit builder recipe
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
|
|
@ -967,4 +972,3 @@ This bit builder recipe configures a build farm host to build an Xilinx VCU118 b
|
|||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
This bit builder recipe configures a build farm host to build an RHS Research Nitefury II bitstream, packaged into a ``bitstream_tar``.
|
||||
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ Then, do platform-specific init steps for the given ``--platform``.
|
|||
|
||||
.. tab:: All other platforms
|
||||
|
||||
This includes platforms such as: ``xilinx_alveo_u250``, ``xilinx_alveo_u280``, ``xilinx_vcu118``, and ``rhsresearch_nitefury_ii``.
|
||||
This includes platforms such as: ``xilinx_alveo_u200``, ``xilinx_alveo_u250``, ``xilinx_alveo_u280``, ``xilinx_vcu118``, and ``rhsresearch_nitefury_ii``.
|
||||
|
||||
* Setup the ``config_runtime.yaml`` and ``config_build.yaml`` files with externally provisioned run/build farm arguments.
|
||||
|
||||
|
|
@ -271,7 +271,7 @@ RUN FARM WITHOUT PROMPTING FOR CONFIRMATION:
|
|||
firesim terminaterunfarm --forceterminate
|
||||
|
||||
|
||||
The ``--terminatesome=INSTANCE_TYPE:COUNT`` flag additionally allows you to
|
||||
The ``--terminatesome=INSTANCE_TYPE:COUNT`` flag additionally allows you to
|
||||
terminate only some (``COUNT``) of the instances of a particular type
|
||||
(``INSTANCE_TYPE``) in a particular Run Farm.
|
||||
|
||||
|
|
@ -426,4 +426,3 @@ used to run simulations for each FPGA attached to the machine.
|
|||
If you ever change the physical layout of a Run Farm Machine in your Run Farm
|
||||
(e.g., which PCIe slot the FPGAs are attached to), you will need to re-run this
|
||||
command.
|
||||
|
||||
|
|
|
|||
|
|
@ -6,9 +6,9 @@ FireSim Basics
|
|||
FireSim is an open-source
|
||||
FPGA-accelerated full-system hardware simulation platform that makes
|
||||
it easy to validate, profile, and debug RTL hardware implementations
|
||||
at 10s to 100s of MHz. FireSim simplifies co-simulating
|
||||
ASIC RTL with cycle-accurate hardware and software models for other system components (e.g. I/Os). FireSim can productively
|
||||
scale from individual SoC simulations hosted on on-prem FPGAs (e.g., a single Xilinx Alveo board attached to a desktop)
|
||||
at 10s to 100s of MHz. FireSim simplifies co-simulating
|
||||
ASIC RTL with cycle-accurate hardware and software models for other system components (e.g. I/Os). FireSim can productively
|
||||
scale from individual SoC simulations hosted on on-prem FPGAs (e.g., a single Xilinx Alveo board attached to a desktop)
|
||||
to massive datacenter-scale simulations harnessing hundreds of cloud FPGAs (e.g., on Amazon EC2 F1).
|
||||
|
||||
FireSim users across academia and industry (at 20+ institutions) have published
|
||||
|
|
@ -84,26 +84,29 @@ Choose your platform to get started
|
|||
FireSim supports many types of FPGAs and FPGA platforms! Click one of the following links to work through the getting started guide for your particular platform.
|
||||
|
||||
* :doc:`/Getting-Started-Guides/AWS-EC2-F1-Getting-Started/index`
|
||||
|
||||
|
||||
* Status: ✅ All FireSim Features Supported.
|
||||
|
||||
* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U200-FPGAs`
|
||||
|
||||
* Status: ✅ All FireSim Features Supported.
|
||||
|
||||
* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs`
|
||||
|
||||
|
||||
* Status: ✅ All FireSim Features Supported.
|
||||
|
||||
* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U280-FPGAs`
|
||||
|
||||
|
||||
* Status: ✅ All FireSim Features Supported.
|
||||
|
||||
* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-VCU118-FPGAs`
|
||||
|
||||
|
||||
* Status: ✅ All FireSim Features Supported.
|
||||
|
||||
* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/RHS-Research-Nitefury-II-FPGAs`
|
||||
|
||||
|
||||
* Status: ✅ All FireSim Features Supported.
|
||||
|
||||
* :doc:`Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Vitis-FPGAs`
|
||||
|
||||
* Status: ⚠️ DMA-based Bridges Not Supported. The Vitis-based U250 flow is **not recommended** unless you have specific constraints that require using Vitis. Notably, the Vitis-based flow does not support DMA-based FireSim bridges (e.g., TracerV, Synthesizable Printfs, etc.), while the XDMA-based flows support all FireSim features, as shown above. If you're unsure, use the XDMA-based U250 flow instead: :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs`.
|
||||
|
||||
* Status: ⚠️ DMA-based Bridges Not Supported. The Vitis-based U250 flow is **not recommended** unless you have specific constraints that require using Vitis. Notably, the Vitis-based flow does not support DMA-based FireSim bridges (e.g., TracerV, Synthesizable Printfs, etc.), while the XDMA-based flows support all FireSim features, as shown above. If you're unsure, use the XDMA-based U250 flow instead: :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs`.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,18 @@
|
|||
.. |fpga_name| replace:: Xilinx Alveo U200
|
||||
.. |hwdb_entry_name| replace:: ``alveo_u200_firesim_rocket_singlecore_no_nic``
|
||||
.. |hwdb_entry_name_non_code| replace:: alveo_u200_firesim_rocket_singlecore_no_nic
|
||||
.. |builder_name| replace:: Xilinx Vivado
|
||||
.. |bit_builder_path| replace:: ``bit-builder-recipes/xilinx_alveo_u200.yaml``
|
||||
.. |vivado_with_version| replace:: Vivado 2021.1
|
||||
.. |vivado_version_number_only| replace:: 2021.1
|
||||
.. |vivado_default_install_path| replace:: ``/tools/Xilinx/Vivado/2021.1``
|
||||
.. |board_package_install| replace:: Download the ``au200`` board support package directory from https://github.com/Xilinx/open-nic-shell/tree/main/board_files/Xilinx and place the directory in ``/tools/Xilinx/Vivado/2021.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/``.
|
||||
|
||||
Building Your Own Hardware Designs
|
||||
===================================================================
|
||||
|
||||
This section will guide you through building a |fpga_name| FPGA bitstream to run FireSim simulations.
|
||||
|
||||
.. include:: Xilinx-XDMA-Build-Farm-Setup-Template.rst
|
||||
|
||||
.. include:: Xilinx-All-Bitstream-Template.rst
|
||||
|
|
@ -11,6 +11,10 @@
|
|||
.. |fpga_spi_part_number| replace:: ``s25fl256xxxxxx0-spi-x1_x2_x4``
|
||||
.. |fpga_attach_prereq| replace:: into either an open M.2. slot on your machine or into an M.2. to Thunderbolt enclosure (then attach the enclosure to your system via a Thunderbolt cable). We have successfully used this enclosure: https://www.amazon.com/ORICO-Enclosure-Compatible-Thunderbolt-Type-C-M2V01/dp/B08R9DMFFT. Before permanently installing your Nitefury into your M.2. slot or enclosure, ensure that you have attached the ribbon cable that will be used for JTAG to the underside of the board (see step 4 below).
|
||||
.. |jtag_help| replace:: JTAG. For the Nitefury, this requires attaching the 14-pin JTAG adapter included with the board to the board using the included ribbon cable, then attaching a USB to JTAG adapter such as the Digilent HS2: https://digilent.com/shop/jtag-hs2-programming-cable/.
|
||||
.. |extra_mcs| replace:: file from step 7.
|
||||
.. |mcs_info| replace:: Inside, you will find three files; the one we are currently interested in will be called ``firesim.mcs``. Note the full path of this ``firesim.mcs`` file for the next step.
|
||||
.. |dip_switch_extra| replace:: power).
|
||||
.. |nitefury_patch_xdma| replace:: The directory you are now in contains the XDMA kernel module. For the Nitefury to work, we will need to make one modification to the driver. Find the line containing ``#define XDMA_ENGINE_XFER_MAX_DESC``. Change the value on this line from ``0x800`` to ``16``. Then, build and install the driver:
|
||||
.. |jtag_cable_reminder| replace:: Remember to keep the USB cable for JTAG connected at all times when running FireSim simulations (it is used to program the FPGA).
|
||||
|
||||
.. include:: Xilinx-XDMA-Template.rst
|
||||
|
|
|
|||
|
|
@ -0,0 +1,20 @@
|
|||
.. |fpga_name| replace:: Xilinx Alveo U200
|
||||
.. _fpga_name: https://www.xilinx.com/products/boards-and-kits/alveo/u200.html
|
||||
.. |fpga_power_info| replace:: For the U200, this is usually PCIe power coming directly from the system's PSU.
|
||||
.. |hwdb_entry_name| replace:: ``alveo_u200_firesim_rocket_singlecore_no_nic``
|
||||
.. |platform_name| replace:: xilinx_alveo_u200
|
||||
.. |board_name| replace:: au200
|
||||
.. |tool_type| replace:: Xilinx Vivado
|
||||
.. |tool_type_lab| replace:: Xilinx Vivado Lab
|
||||
.. |example_var| replace:: ``XILINX_VIVADO``
|
||||
.. |deploy_manager_code| replace:: ``XilinxAlveoU200InstanceDeployManager``
|
||||
.. |fpga_spi_part_number| replace:: ``mt25qu01g-spi-x1_x2_x4``
|
||||
.. |fpga_attach_prereq| replace:: into an open PCIe slot in the machine.
|
||||
.. |jtag_help| replace:: JTAG.
|
||||
.. |extra_mcs| replace:: file from step 7.
|
||||
.. |mcs_info| replace:: Inside, you will find three files; the one we are currently interested in will be called ``firesim.mcs``. Note the full path of this ``firesim.mcs`` file for the next step.
|
||||
.. |dip_switch_extra| replace:: power).
|
||||
.. |nitefury_patch_xdma| replace:: The directory you are now in contains the XDMA kernel module. Now, let's build and install it:
|
||||
.. |jtag_cable_reminder| replace:: Remember to keep the USB cable for JTAG connected at all times when running FireSim simulations (it is used to program the FPGA).
|
||||
|
||||
.. include:: Xilinx-XDMA-Template.rst
|
||||
|
|
@ -10,7 +10,11 @@
|
|||
.. |deploy_manager_code| replace:: ``XilinxAlveoU250InstanceDeployManager``
|
||||
.. |fpga_spi_part_number| replace:: ``mt25qu01g-spi-x1_x2_x4``
|
||||
.. |fpga_attach_prereq| replace:: into an open PCIe slot in the machine.
|
||||
.. |jtag_help| replace:: JTAG.
|
||||
.. |jtag_help| replace:: JTAG.
|
||||
.. |extra_mcs| replace:: file from step 7.
|
||||
.. |mcs_info| replace:: Inside, you will find three files; the one we are currently interested in will be called ``firesim.mcs``. Note the full path of this ``firesim.mcs`` file for the next step.
|
||||
.. |dip_switch_extra| replace:: power).
|
||||
.. |nitefury_patch_xdma| replace:: The directory you are now in contains the XDMA kernel module. Now, let's build and install it:
|
||||
.. |jtag_cable_reminder| replace:: Remember to keep the USB cable for JTAG connected at all times when running FireSim simulations (it is used to program the FPGA).
|
||||
|
||||
.. include:: Xilinx-XDMA-Template.rst
|
||||
|
|
|
|||
|
|
@ -10,7 +10,11 @@
|
|||
.. |deploy_manager_code| replace:: ``XilinxAlveoU280InstanceDeployManager``
|
||||
.. |fpga_spi_part_number| replace:: ``mt25qu01g-spi-x1_x2_x4``
|
||||
.. |fpga_attach_prereq| replace:: into an open PCIe slot in the machine.
|
||||
.. |jtag_help| replace:: JTAG.
|
||||
.. |jtag_help| replace:: JTAG.
|
||||
.. |extra_mcs| replace:: file from step 7.
|
||||
.. |mcs_info| replace:: Inside, you will find three files; the one we are currently interested in will be called ``firesim.mcs``. Note the full path of this ``firesim.mcs`` file for the next step.
|
||||
.. |dip_switch_extra| replace:: power).
|
||||
.. |nitefury_patch_xdma| replace:: The directory you are now in contains the XDMA kernel module. Now, let's build and install it:
|
||||
.. |jtag_cable_reminder| replace:: Remember to keep the USB cable for JTAG connected at all times when running FireSim simulations (it is used to program the FPGA).
|
||||
|
||||
.. include:: Xilinx-XDMA-Template.rst
|
||||
|
|
|
|||
|
|
@ -8,9 +8,13 @@
|
|||
.. |tool_type_lab| replace:: Xilinx Vivado Lab
|
||||
.. |example_var| replace:: ``XILINX_VIVADO``
|
||||
.. |deploy_manager_code| replace:: ``XilinxVCU118InstanceDeployManager``
|
||||
.. |fpga_spi_part_number| replace:: ``mt25qu01g-spi-x1_x2_x4``
|
||||
.. |fpga_attach_prereq| replace:: into an open PCIe slot in the machine. Also, ensure that the SW16 switches on the FPGA are set to ``0101`` to enable QSPI flashing over JTAG (i.e., ``position 1 = 0``, ``position 2 = 1``, ``position 3 = 0``, and ``position 4 = 1``. Having the switch set to the side of the position label indicates 0.)
|
||||
.. |jtag_help| replace:: JTAG.
|
||||
.. |fpga_spi_part_number| replace:: ``mt25qu01g-spi-x1_x2_x4_x8``
|
||||
.. |mcs_info| replace:: Inside, you will find four files; the ones we are currently interested in will be called ``firesim.mcs`` and ``firesim_secondary.mcs``. Note the full path of the ``firesim.mcs`` and ``firesim_secondary.mcs`` files for the next step.
|
||||
.. |fpga_attach_prereq| replace:: into an open PCIe slot in the machine. Also, ensure that the SW16 switches on the board are set to ``0101`` to enable QSPI flashing over JTAG (i.e., ``position 1 = 0``, ``position 2 = 1``, ``position 3 = 0``, and ``position 4 = 1``. Having the switch set to the side of the position label indicates 0.)
|
||||
.. |jtag_help| replace:: JTAG.
|
||||
.. |extra_mcs| replace:: file from step 7 and for Configuration file 2, choose the ``firesim_secondary.mcs`` file from step 7.
|
||||
.. |dip_switch_extra| replace:: power). Then, set the SW16 switches on the board to ``0001`` to set the board to automatically program the FPGA from the QSPI at boot (i.e., ``position 1 = 0``, ``position 2 = 0``, ``position 3 = 0``, and ``position 4 = 1``. Having the switch set to the side of the position label indicates 0.)
|
||||
.. |nitefury_patch_xdma| replace:: The directory you are now in contains the XDMA kernel module. Now, let's build and install it:
|
||||
.. |jtag_cable_reminder| replace:: If necessary, you can remove the USB cable for JTAG (the FPGA is programmed through PCIe for FireSim simulations on the Xilinx VCU118). However, we still recommend leaving the cable attached, since it will allow you to re-flash the SPI in case there are issues.
|
||||
|
||||
.. include:: Xilinx-XDMA-Template.rst
|
||||
|
|
|
|||
|
|
@ -159,7 +159,7 @@ Now, test that the module can be inserted:
|
|||
|
||||
|
||||
The second command above should have produced output indicating that the XVSEC
|
||||
driver is loaded.
|
||||
driver is loaded.
|
||||
|
||||
Also, make sure you get output for the following (usually, ``/usr/local/sbin/xvsecctl``):
|
||||
|
||||
|
|
@ -187,21 +187,18 @@ Now, let's attach your |fpga_name|_ FPGA(s) to your Run Farm Machines:
|
|||
|
||||
6. Obtain an existing bitstream tar file for your FPGA by opening the ``bitstream_tar`` URL listed
|
||||
under |hwdb_entry_name| in the following file: :gh-file-ref:`deploy/sample-backup-configs/sample_config_hwdb.yaml`.
|
||||
7. Extract the ``.tar.gz`` file to a known location. Inside, you will find
|
||||
three files; the one we are currently interested in will be called
|
||||
``firesim.mcs``. Note the full path of this ``firesim.mcs`` file for the
|
||||
next step.
|
||||
7. Extract the ``.tar.gz`` file to a known location. |mcs_info|
|
||||
|
||||
8. Open Vivado Lab and click "Open Hardware Manager". Then click "Open Target" and "Auto connect".
|
||||
|
||||
9. Right-click on your FPGA and click "Add Configuration Memory Device". For a |fpga_name|_, choose |fpga_spi_part_number|
|
||||
as the Configuration Memory Part. Click "OK" when prompted to program the configuration memory device.
|
||||
|
||||
10. For Configuration file, choose the ``firesim.mcs`` file from step 7.
|
||||
10. For Configuration file, choose the ``firesim.mcs`` |extra_mcs|
|
||||
|
||||
11. Uncheck "Verify" and click OK.
|
||||
|
||||
12. When programming the configuration memory device is completed, power off your machine fully (i.e., the FPGA should completely lose power).
|
||||
12. When programming the configuration memory device is completed, power off your machine fully (i.e., the FPGA should completely lose |dip_switch_extra|
|
||||
|
||||
13. Cold-boot the machine. A cold boot is required for the FPGA to be successfully re-programmed from its flash.
|
||||
|
||||
|
|
@ -215,6 +212,8 @@ If successful, this should show an entry with Xilinx as the manufacturer and
|
|||
two memory regions. There should be one entry
|
||||
for each FPGA you've added to the Run Farm Machine.
|
||||
|
||||
.. note:: |jtag_cable_reminder|
|
||||
|
||||
|
||||
6. Install sshd
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
|
@ -338,12 +337,12 @@ Then, reboot your machine.
|
|||
Finally, let's ensure that the |tool_type_lab| tools are properly sourced in
|
||||
your shell setup (i.e. ``.bashrc``) so that any shell on your Run Farm Machines
|
||||
can use the corresponding programs. The environment variables should be
|
||||
visible to any non-interactive shells that are spawned.
|
||||
visible to any non-interactive shells that are spawned.
|
||||
|
||||
You can check this by running the following on the Manager Machine,
|
||||
replacing ``RUN_FARM_IP`` with ``localhost`` if your Run Farm machine
|
||||
and Manager machine are the same machine, or replacing it with the Run Farm
|
||||
machine's IP address if they are different machines.
|
||||
and Manager machine are the same machine, or replacing it with the Run Farm
|
||||
machine's IP address if they are different machines.
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
|
|
@ -358,4 +357,3 @@ each Run Farm machine, replacing ``RUN_FARM_IP`` with a different Run Farm Machi
|
|||
IP address.
|
||||
|
||||
Congratulations! We've now set up your machine/cluster to run simulations. Click Next to continue with the guide.
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,11 @@
|
|||
.. |fpga_name| replace:: Xilinx Alveo U200
|
||||
.. _fpga_name: https://www.xilinx.com/products/boards-and-kits/alveo/u200.html
|
||||
.. |hwdb_entry_name| replace:: ``alveo_u200_firesim_rocket_singlecore_no_nic``
|
||||
.. |platform_name| replace:: xilinx_alveo_u200
|
||||
.. |board_name| replace:: au200
|
||||
.. |tool_type| replace:: Xilinx Vivado
|
||||
.. |tool_type_lab| replace:: Xilinx Vivado Lab
|
||||
.. |example_var| replace:: ``XILINX_VIVADO``
|
||||
.. |deploy_manager_code| replace:: ``XilinxAlveoU200InstanceDeployManager``
|
||||
|
||||
.. include:: Xilinx-XDMA-Template.rst
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
.. |fpga_type| replace:: Xilinx Alveo U200
|
||||
.. |deploy_manager| replace:: XilinxAlveoU200InstanceDeployManager
|
||||
.. |deploy_manager_code| replace:: ``XilinxAlveoU200InstanceDeployManager``
|
||||
.. |runner| replace:: Xilinx Vivado
|
||||
.. |hwdb_entry_name| replace:: alveo_u200_firesim_rocket_singlecore_no_nic
|
||||
|
||||
.. include:: Running-Single-Node-Simulation-Template.rst
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
.. |fpga_name| replace:: Xilinx Alveo U200 XDMA-based
|
||||
.. |fpga_name_short| replace:: Xilinx Alveo U200
|
||||
.. _fpga_name_short: https://www.xilinx.com/products/boards-and-kits/alveo/u200.html
|
||||
.. |flow_name| replace:: XDMA-based
|
||||
.. |build_type| replace:: Xilinx Vivado
|
||||
|
||||
.. _u200-standard-flow:
|
||||
|
||||
.. include:: Intro-Template.rst
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 3
|
||||
|
||||
Initial-Setup/Xilinx-Alveo-U200
|
||||
Repo-Setup/Xilinx-Alveo-U200
|
||||
Running-Simulations/Running-Single-Node-Simulation-Xilinx-Alveo-U200
|
||||
Building-a-FireSim-Bitstream/Xilinx-Alveo-U200
|
||||
|
|
@ -10,6 +10,7 @@ New to FireSim? Jump to the :doc:`/FireSim-Basics` page for more info.
|
|||
|
||||
FireSim-Basics
|
||||
Getting-Started-Guides/AWS-EC2-F1-Getting-Started/index
|
||||
Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U200-FPGAs
|
||||
Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs
|
||||
Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U280-FPGAs
|
||||
Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-VCU118-FPGAs
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
import subprocess
|
||||
import sys
|
||||
import re
|
||||
import time
|
||||
from pathlib import Path
|
||||
|
||||
from typing import Dict, List
|
||||
|
|
@ -102,6 +103,7 @@ def clear_serr_bits(bus_id: str) -> None:
|
|||
run = subprocess.run(['setpci', '-s', bridgeBDF, 'COMMAND=0000:0100'])
|
||||
if run.returncode != 0:
|
||||
sys.exit(f":ERROR: Unable to clear SERR bit for {bridgeBDF}")
|
||||
time.sleep(1)
|
||||
|
||||
# clear fatal error reporting enable bit in the device control register
|
||||
# https://support.xilinx.com/s/question/0D52E00006hpjPHSAY/dell-r720-poweredge-server-reboots-on-fpga-reprogramming?language=en_US
|
||||
|
|
@ -110,6 +112,7 @@ def clear_fatal_error_reporting_bits(bus_id: str) -> None:
|
|||
run = subprocess.run(['setpci', '-s', bridgeBDF, 'CAP_EXP+8.w=0000:0004'])
|
||||
if run.returncode != 0:
|
||||
sys.exit(f":ERROR: Unable to clear error reporting bit for {bridgeBDF}")
|
||||
time.sleep(1)
|
||||
|
||||
def write_to_linux_device_path(path: Path, data: str = '1\n') -> None:
|
||||
try:
|
||||
|
|
@ -117,6 +120,7 @@ def write_to_linux_device_path(path: Path, data: str = '1\n') -> None:
|
|||
open(path, 'w').write(data)
|
||||
except:
|
||||
sys.exit(f":ERROR: Cannot write to {path} value: {data}")
|
||||
time.sleep(1)
|
||||
|
||||
def remove(bus_id: str) -> None:
|
||||
for devicePaths in get_device_paths(bus_id):
|
||||
|
|
@ -138,6 +142,7 @@ def enable_memmapped_transfers(bus_id: str) -> None:
|
|||
run = subprocess.run(['setpci', '-s', deviceBDF, 'COMMAND=0x02'])
|
||||
if run.returncode != 0:
|
||||
sys.exit(f":ERROR: Unable to enable memmapped transfers on {deviceBDF}")
|
||||
time.sleep(1)
|
||||
|
||||
def any_device_exists(bus_id: str) -> bool:
|
||||
return len(get_device_paths(bus_id)) > 0
|
||||
|
|
|
|||
|
|
@ -82,3 +82,4 @@ vivado -mode batch -source ../tcl/build.tcl -tclargs $FREQUENCY $STRATEGY $BOARD
|
|||
mkdir -p ../vivado_proj
|
||||
cp example_pblock_partition_partial.bit ../vivado_proj/firesim.bit
|
||||
cp ../../shell/prebuilt/empty_primary.mcs ../vivado_proj/firesim.mcs
|
||||
cp ../../shell/prebuilt/empty_secondary.mcs ../vivado_proj/firesim_secondary.mcs
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
import Tests._
|
||||
|
||||
val chiselVersion = "3.5.6"
|
||||
val chiselVersion = "3.6.0"
|
||||
|
||||
// keep chisel/firrtl specific class files, rename other conflicts
|
||||
val chiselFirrtlMergeStrategy = CustomMergeStrategy.rename { dep =>
|
||||
|
|
|
|||
|
|
@ -99,7 +99,6 @@ object SimUtils {
|
|||
// Simple wrapper for nested bundles.
|
||||
private class BundleRecord(elms: Seq[(String, Data)]) extends Record {
|
||||
override val elements = ListMap((elms.map { case (name, data) => name -> data.cloneType }):_*)
|
||||
override def cloneType: this.type = new BundleRecord(elms).asInstanceOf[this.type]
|
||||
override def toString: String = s"{${elements.map({case (name, data) => s"${name}: ${data}"}).mkString(", ")}}"
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -192,7 +192,6 @@ abstract class ChannelizedWrapperIO(val config: SimWrapperConfig)
|
|||
|
||||
class ClockRecord(numClocks: Int) extends Record {
|
||||
override val elements = ListMap(Seq.tabulate(numClocks)(i => s"_$i" -> Clock()):_*)
|
||||
override def cloneType = new ClockRecord(numClocks).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
class TargetBoxIO(config: SimWrapperConfig) extends ChannelizedWrapperIO(config) {
|
||||
|
|
@ -212,7 +211,6 @@ class TargetBoxIO(config: SimWrapperConfig) extends ChannelizedWrapperIO(config)
|
|||
override val elements = ListMap((Seq(clockElement) ++ wireElements ++ rvElements):_*) ++
|
||||
// Untokenized ports
|
||||
ListMap("hostClock" -> hostClock, "hostReset" -> hostReset)
|
||||
override def cloneType: this.type = new TargetBoxIO(config).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
class TargetBox(config: SimWrapperConfig) extends BlackBox {
|
||||
|
|
@ -229,7 +227,6 @@ class SimWrapperChannels(config: SimWrapperConfig) extends ChannelizedWrapperIO(
|
|||
}).get
|
||||
|
||||
override val elements = ListMap((Seq(clockElement) ++ wireElements ++ rvElements):_*)
|
||||
override def cloneType: this.type = new SimWrapperChannels(config).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -14,7 +14,6 @@ class AssertBridgeRecord(assertPortName: String, resetPortName: String, numAsser
|
|||
val asserts = Output(UInt(numAsserts.W))
|
||||
val underGlobalReset = Output(Bool())
|
||||
val elements = ListMap(assertPortName -> asserts, resetPortName -> underGlobalReset)
|
||||
override def cloneType = new AssertBridgeRecord(assertPortName, resetPortName, numAsserts).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
case class AssertBridgeParameters(assertPortName: String, resetPortName: String, assertMessages: Seq[String])
|
||||
|
|
|
|||
|
|
@ -56,7 +56,6 @@ class AutoCounterBundle(
|
|||
(triggerName, triggerEnable) +:
|
||||
(resetPortName, underGlobalReset) +:
|
||||
events):_*)
|
||||
override def cloneType = new AutoCounterBundle(eventMetadata, triggerName, resetPortName).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
case class AutoCounterParameters(eventMetadata: Seq[EventMetadata], triggerName: String, resetPortName: String)
|
||||
|
|
|
|||
|
|
@ -33,8 +33,6 @@ class HostPortIO[+T <: Data](private val targetPortProto: T) extends Record with
|
|||
|
||||
val elements = collection.immutable.ListMap(Seq("fromHost" -> fromHost, "toHost" -> toHost, "hBits" -> hBits):_*)
|
||||
|
||||
override def cloneType: this.type = new HostPortIO(targetPortProto).asInstanceOf[this.type]
|
||||
|
||||
private[midas] def getClock(): Clock = {
|
||||
val allTargetClocks = SimUtils.findClocks(targetPortProto)
|
||||
require(allTargetClocks.nonEmpty,
|
||||
|
|
|
|||
|
|
@ -180,7 +180,6 @@ class PeekPokeTokenizedIO(private val targetIO: PeekPokeTargetIO) extends Record
|
|||
val outs = targetOutputs.map({ case (field, name) => name -> InputChannel(field) })
|
||||
val ins = targetInputs.map({ case (field, name) => name -> OutputChannel(field) })
|
||||
override val elements = ListMap((ins ++ outs):_*)
|
||||
override def cloneType = new PeekPokeTokenizedIO(targetIO).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
object PeekPokeTokenizedIO {
|
||||
|
|
@ -210,7 +209,6 @@ class PeekPokeTargetIO(targetIO: Seq[(String, Data)]) extends Record {
|
|||
Seq("clock" -> clock) ++
|
||||
targetIO.map({ case (name, field) => name -> Flipped(chiselTypeOf(field)) })
|
||||
):_*)
|
||||
override def cloneType = new PeekPokeTargetIO(targetIO).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
class PeekPokeBridge(targetIO: Seq[(String, Data)]) extends BlackBox
|
||||
|
|
|
|||
|
|
@ -25,7 +25,6 @@ class PrintRecord(portType: firrtl.ir.BundleType, val formatString: String) exte
|
|||
val enable = Output(Bool())
|
||||
|
||||
val elements = ListMap((Seq("enable" -> enable) ++ args):_*)
|
||||
override def cloneType = new PrintRecord(portType, formatString).asInstanceOf[this.type]
|
||||
|
||||
// Gets the bit position of each argument after the record has been flattened to a UInt
|
||||
def argumentOffsets() = args.foldLeft(Seq(enable.getWidth))({
|
||||
|
|
@ -43,7 +42,6 @@ class PrintRecordBag(resetPortName: String, printPorts: Seq[(firrtl.ir.Port, Str
|
|||
})
|
||||
|
||||
val elements = ListMap(((resetPortName -> underGlobalReset) +: printRecords):_*)
|
||||
override def cloneType = new PrintRecordBag(resetPortName, printPorts).asInstanceOf[this.type]
|
||||
|
||||
// Generates a Bool indicating if at least one Printf has it's enable set on this cycle
|
||||
def hasEnabledPrint(): Bool = printRecords.map(_._2.enable).foldLeft(false.B)(_ || _) && !underGlobalReset
|
||||
|
|
|
|||
|
|
@ -31,7 +31,6 @@ object SerializationUtils {
|
|||
val inputPorts = inputs.map(field => field.name -> Input(field.regenType()))
|
||||
val outputPorts = outputs.map(field => field.name -> Output(field.regenType()))
|
||||
override val elements = immutable.ListMap((inputPorts ++ outputPorts):_*)
|
||||
override def cloneType = new RegeneratedTargetIO(inputs, outputs).asInstanceOf[this.type]
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ class PointerChaserDUT(implicit val p: Parameters) extends Module with HasNastiP
|
|||
|
||||
when (rFire && memoryIF.r.bits.last){
|
||||
resultValid := isFinalNode
|
||||
resultReg := resultReg + memoryIF.r.bits.data.asSInt()
|
||||
resultReg := resultReg + memoryIF.r.bits.data.asSInt
|
||||
}.elsewhen (doneFire) {
|
||||
resultValid := false.B
|
||||
resultReg := 0.S
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
Subproject commit 336f225143590f9060ebe7101e96f235f96db985
|
||||
Subproject commit ffae2aa824295002eed61f2b45ac991eb754b278
|
||||
Loading…
Reference in New Issue