Properly depend on all specified config overlays
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20fd686e33
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@ -103,7 +103,7 @@ ifneq ($(CONFIG_OVERLAY),)
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ifneq ($(shell test -f $(CONFIG_OVERLAY); echo $$?),0)
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$(error Vitis config overlay at $(CONFIG_OVERLAY) does not exist)
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endif
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VPP_CONFIG_OVERLAYS := --config $(abspath $(CONFIG_OVERLAY))
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vpp_config_overlays := $(abspath $(CONFIG_OVERLAY))
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endif
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PROFILE := no
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@ -140,21 +140,22 @@ build_strategy_path = $(STRATEGIES_DIR)/strategy_$(STRATEGY).cfg
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ifneq ($(shell test -f $(build_strategy_path); echo $$?),0)
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$(error Build strategy config at $(build_strategy_path) does not exist)
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endif
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VPP_CONFIG_OVERLAYS += --config $(build_strategy_path)
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vpp_config_overlays += $(build_strategy_path)
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vpp_config_overlay_args = $(addprefix --config ,$(vpp_config_overlays))
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# link and package the xclbin
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%/$(PROJECT_NAME).link.xclbin: %/$(PROJECT_NAME).xo $(build_strategy_path)
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%/$(PROJECT_NAME).link.xclbin: %/$(PROJECT_NAME).xo $(vpp_config_overlays)
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mkdir -p $(@D)
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# Move into temp directory to avoid polluting top-level workdir
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cd $(@D)/..; $(VPP) $(VPP_CONFIG_OVERLAYS) $(VPP_TARGET_SPECIFIC_ARGS) $(VPP_COMMON_ARGS) \
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cd $(@D)/..; $(VPP) $(vpp_config_overlay_args) $(VPP_TARGET_SPECIFIC_ARGS) $(VPP_COMMON_ARGS) \
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--connectivity.sp $(PROJECT_NAME)_1.host_mem_0:DDR[0] \
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--link $(VPP_LDFLAGS) -o $@ $<
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%/$(BUILD_SUBDIR)/$(PROJECT_NAME).xclbin: %/$(TEMP_SUBDIR)/$(PROJECT_NAME).link.xclbin $(build_strategy_path)
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%/$(BUILD_SUBDIR)/$(PROJECT_NAME).xclbin: %/$(TEMP_SUBDIR)/$(PROJECT_NAME).link.xclbin $(vpp_config_overlays)
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mkdir -p $(@D)
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# Move into temp directory to avoid polluting top-level workdir
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cd $(@D)/..; $(VPP) $(VPP_CONFIG_OVERLAYS) $(VPP_TARGET_SPECIFIC_ARGS) $(VPP_COMMON_ARGS) --package --package.out_dir $(PACKAGE_OUT) -o $@ $<
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cd $(@D)/..; $(VPP) $(vpp_config_overlay_args) $(VPP_TARGET_SPECIFIC_ARGS) $(VPP_COMMON_ARGS) --package --package.out_dir $(PACKAGE_OUT) -o $@ $<
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# FPGA-level simulation support
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driver_bin = FireSim-vitis
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@ -14,10 +14,9 @@ prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=true
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prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE=Explore
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prop=run.impl_1.STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED=true
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prop=run.impl_1.STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE=AggressiveExplore
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prop=run.impl_1.{STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.MORE OPTIONS}={-sll_reg_hold_fix}
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# See Note 1
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prop=run.impl_1.{STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.MORE OPTIONS}={-sll_reg_hold_fix}
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# Note 1. There was .5ns skew between the source and destination clock on a
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# path that spanned two SLRs, just as the critical warning gauged.. I've
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