Bring up assertion synthesis
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@ -1 +1 @@
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Subproject commit aee6d33a41cca65a9ebaa10245b9f5d443ecada8
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Subproject commit 292aab91a84970a8a78e4892a9db4c9502afafb8
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@ -330,10 +330,10 @@ uint64_t host_mem_offset = -0x80000000LL;
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// There can only be one instance of assert and print widgets as their IO is
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// uniquely generated by a FIRRTL transform
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#ifdef ASSERTIONWIDGET_struct_guard
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#ifdef ASSERTIONWIDGET_0_PRESENT
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ASSERTIONWIDGET_0_substruct_create;
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add_endpoint(new synthesized_assertions_t(this, ASSERTIONWIDGET_0_substruct));
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#ifdef MIDASASSERTS_struct_guard
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#ifdef MIDASASSERTS_PRESENT
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MIDASASSERTS_substruct_create;
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add_endpoint(new synthesized_assertions_t(this, MIDASASSERTS_substruct));
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#endif
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#endif
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@ -8,8 +8,8 @@ class AssertModule_t: virtual simif_t
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public:
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synthesized_assertions_t * assert_endpoint;
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AssertModule_t(int argc, char** argv) {
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ASSERTIONWIDGET_0_substruct_create;
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assert_endpoint = new synthesized_assertions_t(this, ASSERTIONWIDGET_0_substruct);
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MIDASASSERTS_substruct_create;
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assert_endpoint = new synthesized_assertions_t(this, MIDASASSERTS_substruct);
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};
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void run() {
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int assertions_thrown = 0;
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@ -11,7 +11,7 @@ class NoConfig extends Config(Parameters.empty)
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// This is incomplete and must be mixed into a complete platform config
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class DefaultF1Config extends Config(new Config((site, here, up) => {
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case firesim.util.DesiredHostFrequency => 75
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case SynthAsserts => false
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case SynthAsserts => true
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case midas.GenerateMultiCycleRamModels => true
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case SynthPrints => false
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}) ++ new Config(new firesim.firesim.WithDefaultMemModel ++ new midas.F1Config))
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