Merge remote-tracking branch 'origin/dev'. Needs CY bump.

2020-10-16 23:19:48 +00:00 · 2020-10-16 23:19:48 +00:00 · 44649158c0
parent 01a0d01c9a 830439a659
commit 44649158c0
16 changed files with 56 additions and 44 deletions
--- a/deploy/sample-backup-configs/sample_config_build_recipes.ini
+++ b/deploy/sample-backup-configs/sample_config_build_recipes.ini
@ -13,14 +13,14 @@
 # Quad-core, Rocket-based recipes
 [firesim-rocket-quadcore-nic-l2-llc4mb-ddr3]
 DESIGN=FireSim
-TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig
+TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.QuadRocketConfig
 PLATFORM_CONFIG=F90MHz_BaseF1Config
 instancetype=z1d.2xlarge
 deploytriplet=None

 [firesim-rocket-quadcore-no-nic-l2-llc4mb-ddr3]
 DESIGN=FireSim
-TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig
+TARGET_CONFIG=DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.QuadRocketConfig
 PLATFORM_CONFIG=F90MHz_BaseF1Config
 instancetype=z1d.2xlarge
 deploytriplet=None
@ -29,14 +29,14 @@ deploytriplet=None
 # Single-core, BOOM-based recipes
 [firesim-boom-singlecore-nic-l2-llc4mb-ddr3]
 DESIGN=FireSim
-TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig
+TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomConfig
 PLATFORM_CONFIG=F65MHz_BaseF1Config
 instancetype=z1d.2xlarge
 deploytriplet=None

 [firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3]
 DESIGN=FireSim
-TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig
+TARGET_CONFIG=DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomConfig
 PLATFORM_CONFIG=F70MHz_BaseF1Config
 instancetype=z1d.2xlarge
 deploytriplet=None
@ -45,7 +45,7 @@ deploytriplet=None
 # Single-core, Ariane-based recipes
 [firesim-ariane-singlecore-no-nic-l2-llc4mb-ddr3]
 DESIGN=FireSim
-TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimArianeConfig
+TARGET_CONFIG=DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.ArianeConfig
 PLATFORM_CONFIG=F90MHz_BaseF1Config
 instancetype=z1d.2xlarge
 deploytriplet=None
@ -54,7 +54,7 @@ deploytriplet=None
 # Single-core, Rocket-based recipes with Gemmini
 [firesim-rocket-singlecore-gemmini-no-nic-l2-llc4mb-ddr3]
 DESIGN=FireSim
-TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimGemminiRocketConfig
+TARGET_CONFIG=DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.GemminiRocketConfig
 PLATFORM_CONFIG=F110MHz_BaseF1Config
 instancetype=z1d.2xlarge
 deploytriplet=None
@ -63,7 +63,7 @@ deploytriplet=None
 # RAM Optimizations enabled by adding _MCRams PLATFORM_CONFIG string
 [firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3-ramopts]
 DESIGN=FireSim
-TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig
+TARGET_CONFIG=DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomConfig
 PLATFORM_CONFIG=MCRams_F90MHz_BaseF1Config
 instancetype=z1d.2xlarge
 deploytriplet=None
@ -80,7 +80,7 @@ deploytriplet=None
 # Multiclock Temporary Example:ncept Quad-core, Rocket-based recipes
 [firesim-rocket-singlecore-no-nic-l2-llc4mb-ddr3-half-freq-uncore]
 DESIGN=FireSim
-TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimMulticlockRocketConfig
+TARGET_CONFIG=DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.DividedClockRocketConfig
 PLATFORM_CONFIG=F90MHz_BaseF1Config
 instancetype=z1d.2xlarge
 deploytriplet=None
@ -93,5 +93,3 @@ TARGET_CONFIG=NoConfig
 PLATFORM_CONFIG=DefaultF1Config
 instancetype=z1d.2xlarge
 deploytriplet=None
-
-
--- a/sim/firesim-lib/src/main/scala/configs/FASEDTargetConfigs.scala
+++ b/sim/firesim-lib/src/main/scala/configs/FASEDTargetConfigs.scala
@ -14,7 +14,7 @@ case object DramOrganizationKey extends Field[DramOrganizationParams]

 // Instantiates an AXI4 memory model that executes (1 / clockDivision) of the frequency
 // of the RTL transformed model (Rocket Chip)
-class WithDefaultMemModel(clockDivision: Int = 1) extends Config((site, here, up) => {
+class WithDefaultMemModel extends Config((site, here, up) => {
  case LlcKey => None
  // Only used if a DRAM model is requested
  case DramOrganizationKey => DramOrganizationParams(maxBanks = 8, maxRanks = 4, dramSize = BigInt(1) << 34)
@ -26,9 +26,7 @@ class WithDefaultMemModel(clockDivision: Int = 1) extends Config((site, here, up
    llcKey = site(LlcKey))

  case MemModelKey => new LatencyPipeConfig(site(BaseParamsKey))
-}) {
-  require(clockDivision == 1, "Endpoint clock-division temporarily removed until FireSim 1.8.0")
-}
+})


 /*******************************************************************************
@ -94,12 +92,6 @@ class LBP32R32WLLC4MB extends Config(
  new WithFuncModelLimits(32,32) ++
  new WithDefaultMemModel)

-// An LBP that runs at 1/3 the frequency of the cores + uncore
-// This is 1067 MHz for default core frequency of 3.2 GHz
-class LBP32R32W3Div extends Config(
-  new WithFuncModelLimits(32,32) ++
-  new WithDefaultMemModel(3))
-
 // DDR3 - FCFS models.
 class FCFS16GBQuadRank extends Config(new WithDDR3FIFOMAS(8) ++ new WithDefaultMemModel)
 class FCFS16GBQuadRankLLC4MB extends Config(
@ -107,17 +99,12 @@ class FCFS16GBQuadRankLLC4MB extends Config(
  new FCFS16GBQuadRank)

 // DDR3 - First-Ready FCFS models
-class FRFCFS16GBQuadRank(clockDiv: Int = 1) extends Config(
+class FRFCFS16GBQuadRank extends Config(
  new WithFuncModelLimits(32,32) ++
  new WithDDR3FRFCFS(8, 8) ++
-  new WithDefaultMemModel(clockDiv)
+  new WithDefaultMemModel
 )
 class FRFCFS16GBQuadRankLLC4MB extends Config(
  new WithLLCModel(4096, 8) ++
  new FRFCFS16GBQuadRank
 )
-
-class FRFCFS16GBQuadRankLLC4MB3Div extends Config(
-  new WithLLCModel(4096, 8) ++
-  new FRFCFS16GBQuadRank(3)
-)
--- a/sim/midas/src/main/cc/unittest/Makefrag
+++ b/sim/midas/src/main/cc/unittest/Makefrag
@ -31,7 +31,7 @@ $(GEN_DIR)/$(DESIGN).fir $(GEN_DIR)/$(DESIGN).behav_srams.v: $(scala_srcs)
 		--target-dir $(GEN_DIR) \
 		--name $(DESIGN) \
 		--top-module freechips.rocketchip.unittest.TestHarness \
-		--legacy-configs midas.unittest.$(CONFIG)"
+		--legacy-configs midas.unittest:$(CONFIG)"
 	touch $(GEN_DIR)/$(DESIGN).behav_srams.v

 $(GEN_DIR)/$(DESIGN).v: $(GEN_DIR)/$(DESIGN).fir
--- a/sim/midas/src/main/scala/midas/passes/MidasTransforms.scala
+++ b/sim/midas/src/main/scala/midas/passes/MidasTransforms.scala
@ -64,6 +64,7 @@ private[midas] class MidasTransforms extends Transform {
      ChannelClockInfoAnalysis,
      UpdateBridgeClockInfo,
      fame.WrapTop,
+      fame.LabelMultiThreadedInstances,
      new ResolveAndCheck,
      new EmitFirrtl("post-wrap-top.fir")) ++
    optionalTargetTransforms ++
--- a/sim/midas/src/main/scala/midas/passes/fame/LabelMultiThreadedInstances.scala
+++ b/sim/midas/src/main/scala/midas/passes/fame/LabelMultiThreadedInstances.scala
@ -0,0 +1,31 @@
+// See LICENSE for license details.
+
+package midas.passes.fame
+
+import firrtl._
+
+// This pass labels all instances that are annotated as potential targets for threading as FAME models
+object LabelMultiThreadedInstances extends Transform {
+  def inputForm = HighForm
+  def outputForm = HighForm
+
+  override def execute(state: CircuitState): CircuitState = {
+    val p = state.annotations.collectFirst({ case midas.stage.phases.ConfigParametersAnnotation(p)  => p }).get
+    val enableMultiThreading = p(midas.EnableModelMultiThreading)
+    val fameModelAnnos = new collection.mutable.LinkedHashSet[midas.targetutils.FirrtlFAMEModelAnnotation]
+    val updatedAnnos = state.annotations.flatMap {
+      case fma: midas.targetutils.FirrtlFAMEModelAnnotation =>
+        fameModelAnnos += fma
+        None
+      case f5a @ midas.targetutils.FirrtlEnableModelMultiThreadingAnnotation(it) =>
+        if (enableMultiThreading) {
+          fameModelAnnos += midas.targetutils.FirrtlFAMEModelAnnotation(it)
+          Some(f5a)
+        } else {
+          None
+        }
+      case anno => Some(anno)
+    }
+    state.copy(annotations = AnnotationSeq(updatedAnnos ++ fameModelAnnos))
+  }
+}
--- a/sim/midas/src/main/scala/midas/passes/fame/MultiThreadFAME5Models.scala
+++ b/sim/midas/src/main/scala/midas/passes/fame/MultiThreadFAME5Models.scala
@ -141,8 +141,9 @@ object MultiThreadFAME5Models extends Transform {
    // Populate keys from annotations, values from traversing statements
    val fame5RawInstances = new mutable.LinkedHashMap[OfModule, mutable.LinkedHashSet[Instance]]
    state.annotations.foreach {
-      case FirrtlEnableModelMultiThreadingAnnotation(ModuleTarget(_, m)) =>
-        fame5RawInstances(OfModule(m)) = new mutable.LinkedHashSet[Instance]
+      case FirrtlEnableModelMultiThreadingAnnotation(it) =>
+        // TODO: why not use instance name from here?
+        fame5RawInstances(OfModule(it.ofModule)) = new mutable.LinkedHashSet[Instance]
      case _ =>
    }

--- a/sim/midas/targetutils/src/main/scala/midas/annotations.scala
+++ b/sim/midas/targetutils/src/main/scala/midas/annotations.scala
@ -122,7 +122,8 @@ case class FirrtlFAMEModelAnnotation(
  */
 case class EnableModelMultiThreadingAnnotation(target: BaseModule) extends chisel3.experimental.ChiselAnnotation {
  def toFirrtl: FirrtlEnableModelMultiThreadingAnnotation = {
-    FirrtlEnableModelMultiThreadingAnnotation(target.toNamed.toTarget)
+    val parent = ModuleTarget(target.toNamed.circuit.name, target.parentModName)
+    FirrtlEnableModelMultiThreadingAnnotation(parent.instOf(target.instanceName, target.name))
  }
 }

@ -130,9 +131,9 @@ case class EnableModelMultiThreadingAnnotation(target: BaseModule) extends chise
  * This specifies that the module should be automatically multi-threaded (FIRRTL annotation).
  */
 case class FirrtlEnableModelMultiThreadingAnnotation(
-  target: ModuleTarget) extends SingleTargetAnnotation[ModuleTarget] with FAMEAnnotation {
+  target: InstanceTarget) extends SingleTargetAnnotation[InstanceTarget] with FAMEAnnotation {
  def targets = Seq(target)
-  def duplicate(n: ModuleTarget) = this.copy(n)
+  def duplicate(n: InstanceTarget) = this.copy(n)
 }

 /**
--- a/sim/src/main/makefrag/fasedtests/Makefrag
+++ b/sim/src/main/makefrag/fasedtests/Makefrag
@ -44,7 +44,7 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(chisel_srcs) $(FIRRTL_JAR) $(SCALA_BUILDTOOL_DEPS
 		--target-dir $(GENERATED_DIR) \
 		--name $(long_name) \
 		--top-module $(DESIGN_PACKAGE).$(DESIGN) \
-		--legacy-configs $(TARGET_CONFIG_PACKAGE).$(TARGET_CONFIG))
+		--legacy-configs $(TARGET_CONFIG_PACKAGE):$(TARGET_CONFIG))

 ##########################
 # Driver Sources & Flags #
--- a/sim/src/main/makefrag/firesim/Makefrag
+++ b/sim/src/main/makefrag/firesim/Makefrag
@ -45,7 +45,7 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(FIRRTL_JAR) $(SCALA_BUILDTOOL_DE
 		--target-dir $(GENERATED_DIR) \
 		--name $(long_name) \
 		--top-module $(DESIGN_PACKAGE).$(DESIGN) \
-		--legacy-configs $(TARGET_CONFIG_PACKAGE).$(TARGET_CONFIG))
+		--legacy-configs $(TARGET_CONFIG_PACKAGE):$(TARGET_CONFIG))

 # DOC include start: Bridge Build System Changes
 ##########################
--- a/sim/src/main/makefrag/midasexamples/Makefrag
+++ b/sim/src/main/makefrag/midasexamples/Makefrag
@ -50,7 +50,7 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(chisel_srcs) $(FIRRTL_JAR) $(SCALA_BUILDTOOL_DEPS
 		--target-dir $(GENERATED_DIR) \
 		--name $(long_name) \
 		--top-module $(DESIGN_PACKAGE).$(DESIGN) \
-		--legacy-configs $(TARGET_CONFIG_PACKAGE).$(TARGET_CONFIG))
+		--legacy-configs $(TARGET_CONFIG_PACKAGE):$(TARGET_CONFIG))
 	# Remove once runtime conf generation is generalized, and something is always emitted
 	touch $(GENERATED_DIR)/$(CONF_NAME)

--- a/sim/src/main/scala/midasexamples/MultiReg.scala
+++ b/sim/src/main/scala/midasexamples/MultiReg.scala
@ -29,7 +29,6 @@ class MultiRegDUT extends Module {
  (io.pipeIOs zip pipes).foreach {
    case (pio, p) =>
      p.io <> pio
-      annotate(FAMEModelAnnotation(p))
      annotate(EnableModelMultiThreadingAnnotation(p))
  }
 }
--- a/sim/src/main/scala/midasexamples/MultiRegfile.scala
+++ b/sim/src/main/scala/midasexamples/MultiRegfile.scala
@ -31,7 +31,6 @@ class MultiRegfileDUT extends Module {
  rfs.zip(io.accesses).foreach {
    case (rf, rfio) =>
      rf.io <> rfio
-      annotate(FAMEModelAnnotation(rf))
      annotate(EnableModelMultiThreadingAnnotation(rf))
  }
 }
--- a/sim/src/main/scala/midasexamples/MultiSRAM.scala
+++ b/sim/src/main/scala/midasexamples/MultiSRAM.scala
@ -37,7 +37,6 @@ class MultiSRAMDUT extends Module {
  rfs.zip(io.accesses).foreach {
    case (rf, rfio) =>
      rf.io <> rfio
-      annotate(FAMEModelAnnotation(rf))
      annotate(EnableModelMultiThreadingAnnotation(rf))
  }
 }
--- a/sim/src/main/scala/midasexamples/NestedModels.scala
+++ b/sim/src/main/scala/midasexamples/NestedModels.scala
@ -40,8 +40,6 @@ class NestedModelsDUT extends Module {
  })
  val midA = Module(new Mid)
  val midB = Module(new Mid)
-  annotate(FAMEModelAnnotation(midA))
-  annotate(FAMEModelAnnotation(midB))
  annotate(EnableModelMultiThreadingAnnotation(midA))
  annotate(EnableModelMultiThreadingAnnotation(midB))
  midA.io <> io.a
--- a/sim/src/main/scala/midasexamples/TwoAdders.scala
+++ b/sim/src/main/scala/midasexamples/TwoAdders.scala
@ -44,14 +44,12 @@ class TwoAddersDUT extends Module {
  })

  val a0 = Module(new DoublePipeAdder)
-  annotate(FAMEModelAnnotation(a0))
  annotate(EnableModelMultiThreadingAnnotation(a0))
  a0.io.x := io.i0
  a0.io.y := io.i1
  io.o0 := a0.io.z

  val a1 = Module(new DoublePipeAdder)
-  annotate(FAMEModelAnnotation(a1))
  annotate(EnableModelMultiThreadingAnnotation(a1))
  a1.io.x := io.i2
  a1.io.y := io.i3
--- a/target-design/chipyard
+++ b/target-design/chipyard
@ -1 +1 @@
-Subproject commit 9c8d2948af1c6f82243002b6ae12d10200f4af58
+Subproject commit f3e1cb434d9051c4c4fb119b28f88cf7b8dd4f49