replica
/
firesim
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add SerialBridgeParams scaladoc

This commit is contained in:
Jerry Zhao 2020-09-30 20:48:09 +00:00
parent 42f2652d1d
commit 41c8ce9ac7
2 changed files with 10 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
sim/firesim-lib/src/main/cc/bridges/serial.cc
View File

@ -89,6 +89,7 @@ void serial_t::recv() {
void serial_t::handle_loadmem_read(fesvr_loadmem_t loadmem) {
assert(loadmem.size % sizeof(uint32_t) == 0);
assert(has_mem);
// Loadmem reads are in granularities of the width of the FPGA-DRAM bus
mpz_t buf;
mpz_init(buf);
@ -118,6 +119,7 @@ void serial_t::handle_loadmem_read(fesvr_loadmem_t loadmem) {
void serial_t::handle_loadmem_write(fesvr_loadmem_t loadmem) {
assert(loadmem.size <= 1024);
assert(has_mem);
static char buf[1024];
fesvr->recv_loadmem_data(buf, loadmem.size);
mpz_t data;

8
sim/firesim-lib/src/main/scala/bridges/SerialBridge.scala
View File

@ -10,6 +10,14 @@ import freechips.rocketchip.config.Parameters
import testchipip.{SerialIO, SerialAdapter}
/**
* Class which parameterizes the SerialBridge
*
* memoryRegionNameOpt, if unset, indicates that firesim-fesvr should not attempt to write a payload into DRAM through the loadmem unit.
* This is suitable for target designs which do not use the FASED DRAM model.
* If a FASEDBridge for the backing AXI4 memory is present, then memoryRegionNameOpt should be set to the same memory region name which is passed
* to the FASEDBridge. This enables fast payload loading in firesim-fesvr through the loadmem unit.
*/
case class SerialBridgeParams(memoryRegionNameOpt: Option[String])
class SerialBridge(memoryRegionNameOpt: Option[String]) extends BlackBox with Bridge[HostPortIO[SerialBridgeTargetIO], SerialBridgeModule] {