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Disable metasims right now | Fix build.yaml parsing

This commit is contained in:
abejgonzalez 2023-05-13 12:25:30 -07:00
parent 82a8b58eda
commit 3edc20f0af
3 changed files with 18 additions and 18 deletions
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2
.github/scripts/run-parallel-vcs-metasims.py vendored
View File

@ -58,7 +58,7 @@ def run_parallel_metasim():
else: else:
print(f"Workload {workload} successful.") print(f"Workload {workload} successful.")
run_w_timeout(f"{ci_env['GITHUB_WORKSPACE']}/deploy/workloads/ci/hello-world-localhost-vcs-metasim.yaml", "45m") run_w_timeout(f"{ci_env['REMOTE_WORK_DIR']}/deploy/workloads/ci/hello-world-localhost-vcs-metasim.yaml", "45m")
if __name__ == "__main__": if __name__ == "__main__":
execute(run_parallel_metasim, hosts=["localhost"]) execute(run_parallel_metasim, hosts=["localhost"])

2
.github/scripts/run-xclbin-buildbitstream.py vendored
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@ -65,7 +65,7 @@ def run_xclbin_buildbitstream():
if "- firesim" in line: if "- firesim" in line:
# comment out AWS specific lines # comment out AWS specific lines
byf.write("# " + line + '\n') byf.write("# " + line + '\n')
elif "- {hwdb_entry_to_gen}" in line: elif f"- {hwdb_entry_to_gen}" in line:
# remove comment # remove comment
byf.write(line.replace("# ", '') + '\n') byf.write(line.replace("# ", '') + '\n')
elif 'default_build_dir:' in line: elif 'default_build_dir:' in line:

32
.github/workflows/firesim-run-tests.yml vendored
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@ -440,22 +440,22 @@ jobs:
- name: Check Vitis docs components that require manual re-generation (e.g. config_runtime.yaml example) - name: Check Vitis docs components that require manual re-generation (e.g. config_runtime.yaml example)
run: ./.github/scripts/check-vitis-docs-generated-components.py run: ./.github/scripts/check-vitis-docs-generated-components.py
run-parallel-vcs-metasims-and-vitis-driver: #run-parallel-vcs-metasims-and-vitis-driver:
name: run-parallel-vcs-metasims-and-vitis-driver # name: run-parallel-vcs-metasims-and-vitis-driver
needs: [setup-local-fpga-repo] # needs: [setup-local-fpga-repo]
runs-on: local-fpga # runs-on: local-fpga
steps: # steps:
# This forces a fresh clone of the repo during the `checkout` step # # This forces a fresh clone of the repo during the `checkout` step
# to resolve stale submodule URLs. See https://github.com/ucb-bar/chipyard/pull/1156. # # to resolve stale submodule URLs. See https://github.com/ucb-bar/chipyard/pull/1156.
- name: Delete old checkout # - name: Delete old checkout
run: | # run: |
rm -rf ${{ github.workspace }}/* || true # rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true # rm -rf ${{ github.workspace }}/.* || true
- uses: actions/checkout@v3 # - uses: actions/checkout@v3
- name: Run parallel VCS metasims # - name: Run parallel VCS metasims
run: .github/scripts/run-parallel-vcs-metasims.py # run: .github/scripts/run-parallel-vcs-metasims.py
- name: Build Vitis driver # - name: Build Vitis driver
run: .github/scripts/build-vitis-driver.py # run: .github/scripts/build-vitis-driver.py
run-basic-linux-poweroff-vitis: run-basic-linux-poweroff-vitis:
if: contains(github.event.pull_request.labels.*.name, 'ci:fpga-deploy') if: contains(github.event.pull_request.labels.*.name, 'ci:fpga-deploy')