From 2ea09c9cc951961ca055f3d15dcc50d43bf1878b Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 30 Nov 2021 23:16:43 +0000 Subject: [PATCH] [fased] Add assertions for some LBP overflow conditions --- .../main/scala/midas/models/dram/LatencyBandwidthPipe.scala | 3 +++ sim/midas/src/main/scala/midas/models/dram/TimingModel.scala | 2 ++ 2 files changed, 5 insertions(+) diff --git a/sim/midas/src/main/scala/midas/models/dram/LatencyBandwidthPipe.scala b/sim/midas/src/main/scala/midas/models/dram/LatencyBandwidthPipe.scala index fa5fca5b..2fde0e13 100644 --- a/sim/midas/src/main/scala/midas/models/dram/LatencyBandwidthPipe.scala +++ b/sim/midas/src/main/scala/midas/models/dram/LatencyBandwidthPipe.scala @@ -67,6 +67,7 @@ class LatencyPipe(cfg: LatencyPipeConfig)(implicit p: Parameters) extends SplitT wResp.bits := writePipe.io.deq.bits.xaction writePipe.io.deq.ready := wResp.ready && writeDone + assert(writePipe.io.enq.ready || !newWReq, "LBP write latency pipe would overflow.") // ***** Read Latency Pipe ***** val readPipe = Module(new Queue(new ReadPipeEntry, cfg.maxReads, flow = true)) @@ -79,5 +80,7 @@ class LatencyPipe(cfg: LatencyPipeConfig)(implicit p: Parameters) extends SplitT rResp.valid := readPipe.io.deq.valid && readDone rResp.bits := readPipe.io.deq.bits.xaction readPipe.io.deq.ready := rResp.ready && readDone + + assert(readPipe.io.enq.ready || !nastiReq.ar.fire, "LBP read latency pipe would overflow.") } diff --git a/sim/midas/src/main/scala/midas/models/dram/TimingModel.scala b/sim/midas/src/main/scala/midas/models/dram/TimingModel.scala index 7bba2644..db71d736 100644 --- a/sim/midas/src/main/scala/midas/models/dram/TimingModel.scala +++ b/sim/midas/src/main/scala/midas/models/dram/TimingModel.scala @@ -241,4 +241,6 @@ abstract class SplitTransactionModel(cfg: BaseConfig)(implicit p: Parameters) awQueue.io.enq.bits := nastiReq.aw.bits awQueue.io.enq.valid := nastiReq.aw.fire() awQueue.io.deq.ready := newWReq + assert(awQueue.io.enq.ready || !nastiReq.aw.fire, + "AW queue in SplitTransaction timing model would overflow.") }