[fased] Add assertions for some LBP overflow conditions

sim/midas/src/main/scala/midas/models/dram/LatencyBandwidthPipe.scala

@@ -67,6 +67,7 @@ class LatencyPipe(cfg: LatencyPipeConfig)(implicit p: Parameters) extends SplitT
   wResp.bits := writePipe.io.deq.bits.xaction
   writePipe.io.deq.ready := wResp.ready && writeDone
 
+  assert(writePipe.io.enq.ready || !newWReq, "LBP write latency pipe would overflow.")
 
   // ***** Read Latency Pipe *****
   val readPipe = Module(new Queue(new ReadPipeEntry, cfg.maxReads, flow = true))
@@ -79,5 +80,7 @@ class LatencyPipe(cfg: LatencyPipeConfig)(implicit p: Parameters) extends SplitT
   rResp.valid := readPipe.io.deq.valid && readDone
   rResp.bits := readPipe.io.deq.bits.xaction
   readPipe.io.deq.ready := rResp.ready && readDone
+
+  assert(readPipe.io.enq.ready || !nastiReq.ar.fire, "LBP read latency pipe would overflow.")
 }
 

sim/midas/src/main/scala/midas/models/dram/TimingModel.scala

@@ -241,4 +241,6 @@ abstract class SplitTransactionModel(cfg: BaseConfig)(implicit p: Parameters)
   awQueue.io.enq.bits := nastiReq.aw.bits
   awQueue.io.enq.valid := nastiReq.aw.fire()
   awQueue.io.deq.ready := newWReq
+  assert(awQueue.io.enq.ready || !nastiReq.aw.fire,
+    "AW queue in SplitTransaction timing model would overflow.")
 }