fix TRACEFILE names

deploy/runtools/runtime_config.py

@@ -100,8 +100,9 @@ class RuntimeHWConfig:
         pre-built runtime config? It kinda contains a mix of pre-built and
         runtime parameters currently. """
 
-        tracefile = "+tracefile0=TRACEFILE" if trace_enable else ""
-        autocounterfile = "+autocounter-filename0=AUTOCOUNTERFILE"
+        # TODO: supernode support
+        tracefile = "+tracefile0=TRACEFILE0" if trace_enable else ""
+        autocounterfile = "+autocounter-filename0=AUTOCOUNTERFILE0"
 
         # this monstrosity boots the simulator, inside screen, inside script
         # the sed is in there to get rid of newlines in runtime confs

docs/Advanced-Usage/Debugging-and-Profiling-on-FPGA/AutoCounter.rst

@@ -84,7 +84,7 @@ By default, the read-rate is set to 0 cycles, which is equivalent to disabling A
 
 
 Now when you run a workload, an AutoCounter output file will be placed in the
-`sim_slot_<slot #>` directory on the F1 instance under the name AUTOCOUNTERFILE.
+`sim_slot_<slot #>` directory on the F1 instance under the name AUTOCOUNTERFILE0.
 
 .. Note:: AutoCounter is designed as a coarse-grained observability mechanism. It assumes the counters will be read at intervals greater than O(10000) cycles. If you intend on reading counters at a finer granularity, please consider using synthesizable printfs (otherwise, simulation performance may degrade more than necessary)
 

docs/Advanced-Usage/Debugging-and-Profiling-on-FPGA/TracerV.rst

@@ -37,11 +37,16 @@ instead of ``no``:
     enable=yes
 
 Now when you run a workload, a trace output file will be placed in the
-````sim_slot_<slot #>```` directory on the F1 instance under the name ``TRACEFILE0``.
-You can add ``TRACEFILE0`` to your ``common_simulation_outputs`` or
-``simulation_outputs`` in your workload ``.json`` file to have this automatically
-copied back to your manager.  See the :ref:`defining-custom-workloads` section
-for more information about these options.
+``sim_slot_<slot #>`` directory on the F1 instance under the name ``TRACEFILE0-C0``.
+The first ``0`` in this filename disambiguates between multiple SoCs on one FPGA
+if you're running in supernode mode and will always be ``0`` if you're not running
+in supernode mode. The ``C0`` represents core 0 in the simulated
+SoC. If you have multiple cores, each will have its own file (ending in ``C1``,
+``C2``, etc).  To copy all TracerV trace files back to your manager, you can
+add ``TRACEFILE*`` to your ``common_simulation_outputs`` or
+``simulation_outputs`` in your workload ``.json`` file. See the
+:ref:`defining-custom-workloads` section for more information about these
+options.
 
 Selecting a Trace Output Format
 ---------------------------------

sim/firesim-lib/src/main/cc/bridges/tracerv.cc

@@ -103,7 +103,7 @@ tracerv_t::tracerv_t(
     if (tracefilename) {
         // giving no tracefilename means we will create NO tracefiles
         for (int i = 0; i < NUM_CORES; i++) {
-            std::string tfname = std::string(tracefilename) + std::to_string(i);
+            std::string tfname = std::string(tracefilename) + std::to_string("-C") + std::to_string(i);
             this->tracefiles[i] = fopen(tfname.c_str(), "w");
             if (!this->tracefiles[i]) {
                 fprintf(stderr, "Could not open Trace log file: %s\n", tracefilename);