diff --git a/deploy/runtools/runtime_config.py b/deploy/runtools/runtime_config.py
index 7b1c3d19..4377a199 100644
--- a/deploy/runtools/runtime_config.py
+++ b/deploy/runtools/runtime_config.py
@@ -641,8 +641,10 @@ class RuntimeBuildRecipeConfig(RuntimeHWConfig):
         full_extra_plusargs = " " + self.metasimulation_only_plusargs + " " + extra_plusargs
         if self.metasim_host_simulator in ['vcs', 'vcs-debug']:
             full_extra_plusargs = " " + self.metasimulation_only_vcs_plusargs + " " +  full_extra_plusargs
-        if self.metasim_host_simulator in ['verilator-debug', 'vcs-debug']:
-            full_extra_plusargs += " +waveform=metasim_waveform.vpd "
+        if self.metasim_host_simulator == 'verilator-debug':
+            full_extra_plusargs += " +waveformfile=metasim_waveform.vcd "
+        if self.metasim_host_simulator == 'vcs-debug':
+            full_extra_plusargs += " +fsdbfile=metasim_waveform.fsdb "
         # TODO: spike-dasm support
         full_extra_args = " 2> metasim_stderr.out " + extra_args
         return super(RuntimeBuildRecipeConfig, self).get_boot_simulation_command(
diff --git a/sim/midas/src/main/cc/rtlsim/Makefrag-xcelium b/sim/midas/src/main/cc/rtlsim/Makefrag-xcelium
index eb57b926..6d79ec15 100644
--- a/sim/midas/src/main/cc/rtlsim/Makefrag-xcelium
+++ b/sim/midas/src/main/cc/rtlsim/Makefrag-xcelium
@@ -7,7 +7,7 @@
 
 define CAD_INFO_HEADER
 # --------------------------------------------------------------------------------
-# This script was written and developed by Chipyard at UC Berkeley; however, the
+# This script was written and developed by FireSim at UC Berkeley; however, the
 # underlying commands and reports are copyrighted by Cadence. We thank Cadence for
 # granting permission to share our research to help promote and foster the next
 # generation of innovators.