Register the new ILA transform
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dcd50ada66
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@ -59,11 +59,6 @@ class WithEC2F1Artefacts extends Config((site, here, up) => {
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case HostTransforms => Dependency(firesim.passes.EC2F1Artefacts) +: up(HostTransforms, site)
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})
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// Implements the AutoILA feature on EC2 F1
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class WithILATopWiringTransform extends Config((site, here, up) => {
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case firesim.passes.ILADepthKey => 1024
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case HostTransforms => Dependency[firesim.passes.ILATopWiringTransform] +: up(HostTransforms, site)
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})
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// Tells ILATopWiringTransform to actually populate the ILA
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class WithAutoILA extends Config((site, here, up) => {
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@ -85,6 +80,5 @@ class BaseF1Config extends Config(
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new WithWiringTransform ++
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new WithAsyncResetReplacement ++
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new WithEC2F1Artefacts ++
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new WithILATopWiringTransform ++
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new midas.F1Config
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)
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@ -55,6 +55,7 @@ class GoldenGateCompilerPhase extends Phase {
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// Lower simulator RTL and run user-requested host-transforms
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val hostLoweringCompiler = new Compiler(
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Seq(
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Dependency(midas.passes.AutoILATransform),
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Dependency(midas.passes.HostClockWiring),
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Dependency[firrtl.passes.memlib.SeparateWriteClocks],
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Dependency[firrtl.passes.memlib.SetDefaultReadUnderWrite],
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@ -23,7 +23,6 @@ class DefaultF1Config extends Config(new Config((site, here, up) => {
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new firesim.configs.WithEC2F1Artefacts ++
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new WithDefaultMemModel ++
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new WithWiringTransform ++
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new firesim.configs.WithILATopWiringTransform ++
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new midas.F1Config))
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class PointerChaserConfig extends Config((site, here, up) => {
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@ -195,8 +195,7 @@ repo_state := $(fpga_work_dir)/design/repo_state
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# Enumerates the subset of generated files that must be copied over for FPGA compilation
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fpga_delivery_files = $(addprefix $(fpga_work_dir)/design/$(BASE_FILE_NAME), \
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.sv .defines.vh .env.tcl \
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.synthesis.xdc .implementation.xdc \
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.ila_insert_inst.v .ila_insert_ports.v .ila_insert_wires.v .ila_insert_vivado.tcl)
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.synthesis.xdc .implementation.xdc )
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$(fpga_work_dir)/stamp: $(shell find $(board_dir)/cl_firesim -name '*')
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mkdir -p $(@D)
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@ -207,6 +206,7 @@ $(repo_state): $(simulator_verilog) $(fpga_work_dir)/stamp
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$(firesim_base_dir)/../scripts/repo_state_summary.sh > $(repo_state)
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$(fpga_work_dir)/design/$(BASE_FILE_NAME)%: $(simulator_verilog) $(fpga_work_dir)/stamp
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cp -f $(GENERATED_DIR)/*.ipgen.tcl $(@D) || true
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cp -f $(GENERATED_DIR)/$(@F) $@
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# Goes as far as setting up the build directory without running the cad job
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