Register the new ILA transform

sim/firesim-lib/src/main/scala/configs/CompilerConfigs.scala

@@ -59,11 +59,6 @@ class WithEC2F1Artefacts extends Config((site, here, up) => {
     case HostTransforms => Dependency(firesim.passes.EC2F1Artefacts) +: up(HostTransforms, site)
 })
 
-// Implements the AutoILA feature on EC2 F1
-class WithILATopWiringTransform extends Config((site, here, up) => {
-  case firesim.passes.ILADepthKey => 1024
-  case HostTransforms => Dependency[firesim.passes.ILATopWiringTransform] +: up(HostTransforms, site)
-})
 
 // Tells ILATopWiringTransform to actually populate the ILA
 class WithAutoILA extends Config((site, here, up) => {
@@ -85,6 +80,5 @@ class BaseF1Config extends Config(
   new WithWiringTransform ++
   new WithAsyncResetReplacement ++
   new WithEC2F1Artefacts ++
-  new WithILATopWiringTransform ++
   new midas.F1Config
 )

sim/midas/src/main/scala/midas/stage/GoldenGateCompilerPhase.scala

@@ -55,6 +55,7 @@ class GoldenGateCompilerPhase extends Phase {
     // Lower simulator RTL and run user-requested host-transforms
     val hostLoweringCompiler = new Compiler(
       Seq(
+          Dependency(midas.passes.AutoILATransform),
           Dependency(midas.passes.HostClockWiring),
           Dependency[firrtl.passes.memlib.SeparateWriteClocks],
           Dependency[firrtl.passes.memlib.SetDefaultReadUnderWrite],

sim/src/main/scala/midasexamples/Config.scala

@@ -23,7 +23,6 @@ class DefaultF1Config extends Config(new Config((site, here, up) => {
   new firesim.configs.WithEC2F1Artefacts ++
   new WithDefaultMemModel ++
   new WithWiringTransform ++
-  new firesim.configs.WithILATopWiringTransform ++
   new midas.F1Config))
 
 class PointerChaserConfig extends Config((site, here, up) => {

sim/target-agnostic.mk

@@ -195,8 +195,7 @@ repo_state     := $(fpga_work_dir)/design/repo_state
 # Enumerates the subset of generated files that must be copied over for FPGA compilation
 fpga_delivery_files = $(addprefix $(fpga_work_dir)/design/$(BASE_FILE_NAME), \
 	.sv .defines.vh .env.tcl \
-	.synthesis.xdc .implementation.xdc \
-	.ila_insert_inst.v .ila_insert_ports.v .ila_insert_wires.v .ila_insert_vivado.tcl)
+	.synthesis.xdc .implementation.xdc )
 
 $(fpga_work_dir)/stamp: $(shell find $(board_dir)/cl_firesim -name '*')
 	mkdir -p $(@D)
@@ -207,6 +206,7 @@ $(repo_state): $(simulator_verilog) $(fpga_work_dir)/stamp
 	$(firesim_base_dir)/../scripts/repo_state_summary.sh > $(repo_state)
 
 $(fpga_work_dir)/design/$(BASE_FILE_NAME)%: $(simulator_verilog) $(fpga_work_dir)/stamp
+	cp -f $(GENERATED_DIR)/*.ipgen.tcl $(@D) || true
 	cp -f $(GENERATED_DIR)/$(@F) $@
 
 # Goes as far as setting up the build directory without running the cad job