Add first DRAM channel to Vitis Shell

sim/firesim-lib/src/main/cc/fesvr/firesim_tsi.cc

@@ -10,7 +10,7 @@ firesim_tsi_t::firesim_tsi_t(int argc, char** argv, bool can_have_loadmem) : tes
     if (arg.find("+idle-counts=") == 0)
       idle_counts = atoi(arg.c_str()+13);
   }
-  has_loadmem = false;
+  has_loadmem = can_have_loadmem;
 }
 
 void firesim_tsi_t::idle()

sim/midas/src/main/cc/simif_vitis.cc

@@ -6,6 +6,8 @@
 #include <sys/types.h>
 #include <unistd.h>
 
+constexpr size_t u250_dram_channel_size_bytes = 16ULL * 1024 * 1024 * 1024;
+
 simif_vitis_t::simif_vitis_t(int argc, char** argv) {
     device_index = -1;
     binary_file = "";
@@ -42,6 +44,14 @@ simif_vitis_t::simif_vitis_t(int argc, char** argv) {
     // Open Kernel
     kernel_handle = xrt::ip(device_handle, uuid, "firesim");
 
+    // Intialize FPGA-DRAM regions.
+    // The final argument here is the bank index for the dram channel.
+    // I used xclbinutil to find this
+    // https://xilinx.github.io/XRT/master/html/xclbintools.html
+    auto fpga_mem_0 = xrt::bo(device_handle, u250_dram_channel_size_bytes, xrt::bo::flags::device_only, 0);
+
+    fprintf(stdout, "fpga_mem_0 offset: %llx\n", fpga_mem_0.address());
+
     fprintf(stdout, "DEBUG: Successfully opened kernel\n");
 
 }

sim/midas/src/main/scala/midas/platform/VitisShim.scala

@@ -9,7 +9,7 @@ import freechips.rocketchip.config.{Parameters, Field}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp}
 import freechips.rocketchip.util.HeterogeneousBag
 
-import midas.core.{DMANastiKey}
+import midas.core.{DMANastiKey, HostMemChannelKey}
 import midas.widgets.{AXI4Printf, CtrlNastiKey}
 import midas.stage.GoldenGateOutputFileAnnotation
 import midas.platform.xilinx._
@@ -17,6 +17,9 @@ import midas.platform.xilinx._
 object VitisConstants {
   // Configurable through v++
   val kernelDefaultFreqMHz = 300.0
+
+  // This is wider than the addresses used in FPGATop
+  val axi4MAddressBits = 64
 }
 
 class VitisShim(implicit p: Parameters) extends PlatformShim {
@@ -25,10 +28,16 @@ class VitisShim(implicit p: Parameters) extends PlatformShim {
     p(CtrlNastiKey).dataBits,
     p(CtrlNastiKey).idBits)
 
+  val hostMemAXI4BundleParams = p(HostMemChannelKey)
+    .axi4BundleParams
+    .copy(addrBits = VitisConstants.axi4MAddressBits)
+
+
   lazy val module = new LazyRawModuleImp(this) {
     val ap_rst_n    = IO(Input(AsyncReset()))
     val ap_clk      = IO(Input(Clock()))
     val s_axi_lite  = IO(Flipped(new XilinxAXI4Bundle(ctrlAXI4BundleParams, isAXI4Lite = true)))
+    val host_mem_0    = IO((new XilinxAXI4Bundle(hostMemAXI4BundleParams)))
 
     val ap_rst = (!ap_rst_n.asBool)
 
@@ -90,6 +99,19 @@ class VitisShim(implicit p: Parameters) extends PlatformShim {
     ctrl_cdc.io.m_axi.driveStandardAXI4(axi4ToNasti.io.axi4, hostClock, hostSyncReset)
     top.module.ctrl <> axi4ToNasti.io.nasti
 
+
+    val host_mem_cdc = Module(new AXI4ClockConverter(hostMemAXI4BundleParams, "host_mem_cdc"))
+    host_mem_cdc.io.s_axi.drivenByStandardAXI4(top.module.mem(0), hostClock, hostSyncReset)
+    host_mem_cdc.io.s_axi_aclk := hostClock
+    host_mem_cdc.io.s_axi_aresetn := (!hostSyncReset).asAsyncReset
+    host_mem_cdc.io.s_axi.araddr := 0x400000000L.U(VitisConstants.axi4MAddressBits.W) + top.module.mem(0).ar.bits.addr
+    host_mem_cdc.io.s_axi.awaddr := 0x400000000L.U(VitisConstants.axi4MAddressBits.W) + top.module.mem(0).aw.bits.addr
+
+    host_mem_0 <> host_mem_cdc.io.m_axi
+    host_mem_cdc.io.m_axi_aclk := ap_clk
+    host_mem_cdc.io.m_axi_aresetn := ap_rst_n
+
+
     GoldenGateOutputFileAnnotation.annotateFromChisel(
       s"// Vitis Shim requires no dynamically generated macros \n",
       fileSuffix = ".defines.vh")

sim/src/main/makefrag/firesim/Makefrag

@@ -8,12 +8,13 @@ DESIGN ?= FireSim
 # These guide chisel elaboration of the target design specified above.
 # See src/main/scala/SimConfigs.scala
 TARGET_CONFIG_PACKAGE ?= firesim.firesim
+#TARGET_CONFIG ?= FireSimNoMemPortConfig
 TARGET_CONFIG ?= FireSimRocketConfig
 
 # These guide chisel elaboration of simulation components by MIDAS, including models and widgets.
 # See src/main/scala/SimConfigs.scala
 PLATFORM_CONFIG_PACKAGE ?= firesim.firesim
-PLATFORM_CONFIG ?= BaseF1Config
+PLATFORM_CONFIG ?= BaseVitisConfig
 
 name_tuple    := $(DESIGN)-$(TARGET_CONFIG)-$(PLATFORM_CONFIG)
 GENERATED_DIR := $(firesim_base_dir)/generated-src/$(PLATFORM)/$(name_tuple)