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firesim/sim/make/post-synth.mk

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VCS post-synthesis RTL simulators (#1438) This PR adds make rules to get the post-synth RTL out of vivado and build a VCS simulator out of it. On VCS, a 150ns startup delay is hard-wired on all simulation modes to yield identical waveforms. The delay is required to initialize vivado gate-level libraries. Co-authored-by: Nandor Licker <nandorl@sifive.com>
2023-02-24 14:06:50 +08:00
# See LICENSE for license details.
Extends tests to work with post-synth RTL (#1439) Includes improvements to post-synth simulations: - Added a `QUICK` strategy which tries to get Vivado to run fast, yet still helps us reproduce failures - Limited Vivado to 1 thread to mitigate flakyness from parallel synthesis - The harness now explicitly waits for GSR - Integrated post-synth metasims with the harness. Setting `TEST_DISABLE_VIVADO=1` in the environment disables these tests even if Vivado is available. Co-authored-by: Nandor Licker <nandorl@sifive.com>
2023-02-28 00:20:01 +08:00
STRATEGY ?= QUICK
VCS post-synthesis RTL simulators (#1438) This PR adds make rules to get the post-synth RTL out of vivado and build a VCS simulator out of it. On VCS, a 150ns startup delay is hard-wired on all simulation modes to yield identical waveforms. The delay is required to initialize vivado gate-level libraries. Co-authored-by: Nandor Licker <nandorl@sifive.com>
2023-02-24 14:06:50 +08:00
FREQUENCY ?= 30
################################################################################
# Post-synthesis RTL generation
################################################################################
POST_SYNTH_RTL := $(GENERATED_DIR)/verilog.sv
Extends tests to work with post-synth RTL (#1439) Includes improvements to post-synth simulations: - Added a `QUICK` strategy which tries to get Vivado to run fast, yet still helps us reproduce failures - Limited Vivado to 1 thread to mitigate flakyness from parallel synthesis - The harness now explicitly waits for GSR - Integrated post-synth metasims with the harness. Setting `TEST_DISABLE_VIVADO=1` in the environment disables these tests even if Vivado is available. Co-authored-by: Nandor Licker <nandorl@sifive.com>
2023-02-28 00:20:01 +08:00
POST_SYNTH_DESIGN_XDC := $(GENERATED_DIR)/$(BASE_FILE_NAME).post-synth.xdc
POST_SYNTH_XDC := $(firesim_base_dir)/scripts/synth_fpga.xdc
VCS post-synthesis RTL simulators (#1438) This PR adds make rules to get the post-synth RTL out of vivado and build a VCS simulator out of it. On VCS, a 150ns startup delay is hard-wired on all simulation modes to yield identical waveforms. The delay is required to initialize vivado gate-level libraries. Co-authored-by: Nandor Licker <nandorl@sifive.com>
2023-02-24 14:06:50 +08:00
Extends tests to work with post-synth RTL (#1439) Includes improvements to post-synth simulations: - Added a `QUICK` strategy which tries to get Vivado to run fast, yet still helps us reproduce failures - Limited Vivado to 1 thread to mitigate flakyness from parallel synthesis - The harness now explicitly waits for GSR - Integrated post-synth metasims with the harness. Setting `TEST_DISABLE_VIVADO=1` in the environment disables these tests even if Vivado is available. Co-authored-by: Nandor Licker <nandorl@sifive.com>
2023-02-28 00:20:01 +08:00
$(POST_SYNTH_DESIGN_XDC): $(simulator_xdc)
sed 's#firesim_top/top/##g' $(simulator_xdc) > $(POST_SYNTH_DESIGN_XDC)
VCS post-synthesis RTL simulators (#1438) This PR adds make rules to get the post-synth RTL out of vivado and build a VCS simulator out of it. On VCS, a 150ns startup delay is hard-wired on all simulation modes to yield identical waveforms. The delay is required to initialize vivado gate-level libraries. Co-authored-by: Nandor Licker <nandorl@sifive.com>
2023-02-24 14:06:50 +08:00
Extends tests to work with post-synth RTL (#1439) Includes improvements to post-synth simulations: - Added a `QUICK` strategy which tries to get Vivado to run fast, yet still helps us reproduce failures - Limited Vivado to 1 thread to mitigate flakyness from parallel synthesis - The harness now explicitly waits for GSR - Integrated post-synth metasims with the harness. Setting `TEST_DISABLE_VIVADO=1` in the environment disables these tests even if Vivado is available. Co-authored-by: Nandor Licker <nandorl@sifive.com>
2023-02-28 00:20:01 +08:00
$(POST_SYNTH_RTL): $(firesim_base_dir)/scripts/synth_fpga.tcl $(POST_SYNTH_XDC) $(POST_SYNTH_DESIGN_XDC) $(simulator_verilog)
VCS post-synthesis RTL simulators (#1438) This PR adds make rules to get the post-synth RTL out of vivado and build a VCS simulator out of it. On VCS, a 150ns startup delay is hard-wired on all simulation modes to yield identical waveforms. The delay is required to initialize vivado gate-level libraries. Co-authored-by: Nandor Licker <nandorl@sifive.com>
2023-02-24 14:06:50 +08:00
cd $(GENERATED_DIR) && time vivado \
-mode batch -nojournal \
-source $(firesim_base_dir)/scripts/synth_fpga.tcl \
Extends tests to work with post-synth RTL (#1439) Includes improvements to post-synth simulations: - Added a `QUICK` strategy which tries to get Vivado to run fast, yet still helps us reproduce failures - Limited Vivado to 1 thread to mitigate flakyness from parallel synthesis - The harness now explicitly waits for GSR - Integrated post-synth metasims with the harness. Setting `TEST_DISABLE_VIVADO=1` in the environment disables these tests even if Vivado is available. Co-authored-by: Nandor Licker <nandorl@sifive.com>
2023-02-28 00:20:01 +08:00
-tclargs $(STRATEGY) $(FREQUENCY) $@ $(wordlist 2,4,$^)
VCS post-synthesis RTL simulators (#1438) This PR adds make rules to get the post-synth RTL out of vivado and build a VCS simulator out of it. On VCS, a 150ns startup delay is hard-wired on all simulation modes to yield identical waveforms. The delay is required to initialize vivado gate-level libraries. Co-authored-by: Nandor Licker <nandorl@sifive.com>
2023-02-24 14:06:50 +08:00
.PHONY: post-synth-rtl
post-synth-rtl: $(POST_SYNTH_RTL)