From 90a19bd058d446c8b38b3cbd9ab6ddba6d3d3de0 Mon Sep 17 00:00:00 2001 From: Daniel Kroening Date: Thu, 1 Feb 2024 11:18:08 -0800 Subject: [PATCH] Verilog: add tests for combiations of declarations This adds tests for combinations of wire/reg/input/output/inout for the same identifier. --- .../verilog/data-types/enum_name_collision.desc | 8 ++++++++ .../verilog/data-types/enum_name_collision.sv | 8 ++++++++ regression/verilog/modules/inout_and_reg.desc | 7 +++++++ regression/verilog/modules/inout_and_reg.v | 5 +++++ .../verilog/modules/input_and_ansi_input.desc | 8 ++++++++ regression/verilog/modules/input_and_ansi_input.v | 4 ++++ regression/verilog/modules/input_and_output.desc | 8 ++++++++ regression/verilog/modules/input_and_output.v | 5 +++++ regression/verilog/modules/input_and_reg.desc | 7 +++++++ regression/verilog/modules/input_and_reg.v | 5 +++++ .../verilog/modules/parameter_name_collision.desc | 7 +++++++ .../verilog/modules/parameter_name_collision.v | 6 ++++++ regression/verilog/modules/wire_and_output.desc | 7 +++++++ regression/verilog/modules/wire_and_output.v | 10 ++++++++++ regression/verilog/modules/wire_and_reg.desc | 8 ++++++++ regression/verilog/modules/wire_and_reg.v | 5 +++++ regression/verilog/modules/wire_and_wire.desc | 8 ++++++++ regression/verilog/modules/wire_and_wire.v | 5 +++++ regression/verilog/tasks/task_name_collision.desc | 9 +++++++++ regression/verilog/tasks/task_name_collision.v | 13 +++++++++++++ .../verilog/typedef/typedef_name_collision1.desc | 8 ++++++++ .../verilog/typedef/typedef_name_collision1.sv | 8 ++++++++ .../verilog/typedef/typedef_name_collision2.desc | 7 +++++++ .../verilog/typedef/typedef_name_collision2.sv | 8 ++++++++ 24 files changed, 174 insertions(+) create mode 100644 regression/verilog/data-types/enum_name_collision.desc create mode 100644 regression/verilog/data-types/enum_name_collision.sv create mode 100644 regression/verilog/modules/inout_and_reg.desc create mode 100644 regression/verilog/modules/inout_and_reg.v create mode 100644 regression/verilog/modules/input_and_ansi_input.desc create mode 100644 regression/verilog/modules/input_and_ansi_input.v create mode 100644 regression/verilog/modules/input_and_output.desc create mode 100644 regression/verilog/modules/input_and_output.v create mode 100644 regression/verilog/modules/input_and_reg.desc create mode 100644 regression/verilog/modules/input_and_reg.v create mode 100644 regression/verilog/modules/parameter_name_collision.desc create mode 100644 regression/verilog/modules/parameter_name_collision.v create mode 100644 regression/verilog/modules/wire_and_output.desc create mode 100644 regression/verilog/modules/wire_and_output.v create mode 100644 regression/verilog/modules/wire_and_reg.desc create mode 100644 regression/verilog/modules/wire_and_reg.v create mode 100644 regression/verilog/modules/wire_and_wire.desc create mode 100644 regression/verilog/modules/wire_and_wire.v create mode 100644 regression/verilog/tasks/task_name_collision.desc create mode 100644 regression/verilog/tasks/task_name_collision.v create mode 100644 regression/verilog/typedef/typedef_name_collision1.desc create mode 100644 regression/verilog/typedef/typedef_name_collision1.sv create mode 100644 regression/verilog/typedef/typedef_name_collision2.desc create mode 100644 regression/verilog/typedef/typedef_name_collision2.sv diff --git a/regression/verilog/data-types/enum_name_collision.desc b/regression/verilog/data-types/enum_name_collision.desc new file mode 100644 index 0000000..76da425 --- /dev/null +++ b/regression/verilog/data-types/enum_name_collision.desc @@ -0,0 +1,8 @@ +KNOWNBUG +enum_name_collision.sv + +^EXIT=2$ +^SIGNAL=0$ +-- +-- +The name collision should be errored. diff --git a/regression/verilog/data-types/enum_name_collision.sv b/regression/verilog/data-types/enum_name_collision.sv new file mode 100644 index 0000000..ceccd1e --- /dev/null +++ b/regression/verilog/data-types/enum_name_collision.sv @@ -0,0 +1,8 @@ +module main; + + typedef enum { some_identifier } some_type; + + // name collision + wire some_identifier; + +endmodule diff --git a/regression/verilog/modules/inout_and_reg.desc b/regression/verilog/modules/inout_and_reg.desc new file mode 100644 index 0000000..3d3f377 --- /dev/null +++ b/regression/verilog/modules/inout_and_reg.desc @@ -0,0 +1,7 @@ +CORE +inout_and_reg.v + +^file .* line 4: symbol `some_var' is declared both as input and as register$ +^EXIT=2$ +^SIGNAL=0$ +-- diff --git a/regression/verilog/modules/inout_and_reg.v b/regression/verilog/modules/inout_and_reg.v new file mode 100644 index 0000000..b68ee11 --- /dev/null +++ b/regression/verilog/modules/inout_and_reg.v @@ -0,0 +1,5 @@ +module main; + // some_var must not be both an input and a reg + inout [31:0] some_var; + reg [31:0] some_var; +endmodule diff --git a/regression/verilog/modules/input_and_ansi_input.desc b/regression/verilog/modules/input_and_ansi_input.desc new file mode 100644 index 0000000..06f084a --- /dev/null +++ b/regression/verilog/modules/input_and_ansi_input.desc @@ -0,0 +1,8 @@ +KNOWNBUG +input_and_ansi_input.v + +^EXIT=2$ +^SIGNAL=0$ +-- +-- +The redeclaration must be errored. diff --git a/regression/verilog/modules/input_and_ansi_input.v b/regression/verilog/modules/input_and_ansi_input.v new file mode 100644 index 0000000..3884a47 --- /dev/null +++ b/regression/verilog/modules/input_and_ansi_input.v @@ -0,0 +1,4 @@ +module main(input [31:0] some_var); + // some_var must not be redeclared + input [31:0] some_var; +endmodule diff --git a/regression/verilog/modules/input_and_output.desc b/regression/verilog/modules/input_and_output.desc new file mode 100644 index 0000000..7f7b300 --- /dev/null +++ b/regression/verilog/modules/input_and_output.desc @@ -0,0 +1,8 @@ +KNOWNBUG +input_and_output.v + +^EXIT=2$ +^SIGNAL=0$ +-- +-- +This should be errored, as some_var must not be both input and output. diff --git a/regression/verilog/modules/input_and_output.v b/regression/verilog/modules/input_and_output.v new file mode 100644 index 0000000..7b050d6 --- /dev/null +++ b/regression/verilog/modules/input_and_output.v @@ -0,0 +1,5 @@ +module main(x); + // cannot declare both as input and output + input [31:0] x; + output [31:0] x; +endmodule diff --git a/regression/verilog/modules/input_and_reg.desc b/regression/verilog/modules/input_and_reg.desc new file mode 100644 index 0000000..fa2b801 --- /dev/null +++ b/regression/verilog/modules/input_and_reg.desc @@ -0,0 +1,7 @@ +CORE +input_and_reg.v + +^file .* line 4: symbol `some_var' is declared both as input and as register$ +^EXIT=2$ +^SIGNAL=0$ +-- diff --git a/regression/verilog/modules/input_and_reg.v b/regression/verilog/modules/input_and_reg.v new file mode 100644 index 0000000..6847cdd --- /dev/null +++ b/regression/verilog/modules/input_and_reg.v @@ -0,0 +1,5 @@ +module main; + // some_var must not be both an input and a reg + input [31:0] some_var; + reg [31:0] some_var; +endmodule diff --git a/regression/verilog/modules/parameter_name_collision.desc b/regression/verilog/modules/parameter_name_collision.desc new file mode 100644 index 0000000..b82431b --- /dev/null +++ b/regression/verilog/modules/parameter_name_collision.desc @@ -0,0 +1,7 @@ +CORE +parameter_name_collision.v + +^file .* line 4: definition of symbol `p' conflicts with earlier definition at line 3$ +^EXIT=2$ +^SIGNAL=0$ +-- diff --git a/regression/verilog/modules/parameter_name_collision.v b/regression/verilog/modules/parameter_name_collision.v new file mode 100644 index 0000000..370e391 --- /dev/null +++ b/regression/verilog/modules/parameter_name_collision.v @@ -0,0 +1,6 @@ +module main; + + parameter p = 123; + parameter p = 123; + +endmodule diff --git a/regression/verilog/modules/wire_and_output.desc b/regression/verilog/modules/wire_and_output.desc new file mode 100644 index 0000000..4194eb4 --- /dev/null +++ b/regression/verilog/modules/wire_and_output.desc @@ -0,0 +1,7 @@ +CORE +wire_and_output.v +--module M1 +^no properties$ +^EXIT=10$ +^SIGNAL=0$ +-- diff --git a/regression/verilog/modules/wire_and_output.v b/regression/verilog/modules/wire_and_output.v new file mode 100644 index 0000000..9a95f3b --- /dev/null +++ b/regression/verilog/modules/wire_and_output.v @@ -0,0 +1,10 @@ +module M1(some_port); + output [31:0] some_port; + wire [31:0] some_port; +endmodule + +module M2(some_port); + // order flipped + wire [31:0] some_port; + output [31:0] some_port; +endmodule diff --git a/regression/verilog/modules/wire_and_reg.desc b/regression/verilog/modules/wire_and_reg.desc new file mode 100644 index 0000000..ecd0f40 --- /dev/null +++ b/regression/verilog/modules/wire_and_reg.desc @@ -0,0 +1,8 @@ +KNOWNBUG +wire_and_reg.v + +^EXIT=2$ +^SIGNAL=0$ +-- +-- +This should be errored, as some_var must not be both wire and reg. diff --git a/regression/verilog/modules/wire_and_reg.v b/regression/verilog/modules/wire_and_reg.v new file mode 100644 index 0000000..fc43de1 --- /dev/null +++ b/regression/verilog/modules/wire_and_reg.v @@ -0,0 +1,5 @@ +module main; + // some_var must not be both wire and reg + wire [31:0] some_var; + reg [31:0] some_var; +endmodule diff --git a/regression/verilog/modules/wire_and_wire.desc b/regression/verilog/modules/wire_and_wire.desc new file mode 100644 index 0000000..6cd0d51 --- /dev/null +++ b/regression/verilog/modules/wire_and_wire.desc @@ -0,0 +1,8 @@ +KNOWNBUG +input_and_reg.v + +^EXIT=2$ +^SIGNAL=0$ +-- +-- +The redeclaration must be errored. diff --git a/regression/verilog/modules/wire_and_wire.v b/regression/verilog/modules/wire_and_wire.v new file mode 100644 index 0000000..5d041fb --- /dev/null +++ b/regression/verilog/modules/wire_and_wire.v @@ -0,0 +1,5 @@ +module main; + // some_var must not be redeclared + wire [31:0] some_var; + wire [31:0] some_var; +endmodule diff --git a/regression/verilog/tasks/task_name_collision.desc b/regression/verilog/tasks/task_name_collision.desc new file mode 100644 index 0000000..1374582 --- /dev/null +++ b/regression/verilog/tasks/task_name_collision.desc @@ -0,0 +1,9 @@ +KNOWNBUG +task_name_collision.v + +^definition of symbol `some_task' conflicts with earlier definition at line$ +^EXIT=2$ +^SIGNAL=0$ +-- +-- +The line number is missing. diff --git a/regression/verilog/tasks/task_name_collision.v b/regression/verilog/tasks/task_name_collision.v new file mode 100644 index 0000000..3ac3f30 --- /dev/null +++ b/regression/verilog/tasks/task_name_collision.v @@ -0,0 +1,13 @@ +module main; + + reg [31:0] data; + + task some_task; + data = 123; + endtask + + task some_task; + data = 456; + endtask + +endmodule diff --git a/regression/verilog/typedef/typedef_name_collision1.desc b/regression/verilog/typedef/typedef_name_collision1.desc new file mode 100644 index 0000000..4837afd --- /dev/null +++ b/regression/verilog/typedef/typedef_name_collision1.desc @@ -0,0 +1,8 @@ +KNOWNBUG +typedef_name_collision1.sv + +^EXIT=2$ +^SIGNAL=0$ +-- +-- +The name collision should be errored. diff --git a/regression/verilog/typedef/typedef_name_collision1.sv b/regression/verilog/typedef/typedef_name_collision1.sv new file mode 100644 index 0000000..c36540e --- /dev/null +++ b/regression/verilog/typedef/typedef_name_collision1.sv @@ -0,0 +1,8 @@ +module main; + + typedef bit some_identifier; + + // name collision + typedef bit some_identifier; + +endmodule diff --git a/regression/verilog/typedef/typedef_name_collision2.desc b/regression/verilog/typedef/typedef_name_collision2.desc new file mode 100644 index 0000000..6922451 --- /dev/null +++ b/regression/verilog/typedef/typedef_name_collision2.desc @@ -0,0 +1,7 @@ +CORE +typedef_name_collision2.sv + +^file .* line 6: definition of symbol `some_identifier' conflicts with earlier definition at line 3$ +^EXIT=2$ +^SIGNAL=0$ +-- diff --git a/regression/verilog/typedef/typedef_name_collision2.sv b/regression/verilog/typedef/typedef_name_collision2.sv new file mode 100644 index 0000000..da78841 --- /dev/null +++ b/regression/verilog/typedef/typedef_name_collision2.sv @@ -0,0 +1,8 @@ +module main; + + wire some_identifier; + + // name collision + typedef bit some_identifier; + +endmodule