From 2713592b1b90ac0fb2a2dcd9cbeada8018b49387 Mon Sep 17 00:00:00 2001 From: Daniel Kroening Date: Thu, 1 Feb 2024 13:15:54 -0800 Subject: [PATCH] Verilog: add source location for function/task symbols --- regression/verilog/tasks/task_name_collision.desc | 5 ++--- src/verilog/verilog_elaborate.cpp | 1 + 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/regression/verilog/tasks/task_name_collision.desc b/regression/verilog/tasks/task_name_collision.desc index 1374582..24eb517 100644 --- a/regression/verilog/tasks/task_name_collision.desc +++ b/regression/verilog/tasks/task_name_collision.desc @@ -1,9 +1,8 @@ -KNOWNBUG +CORE task_name_collision.v -^definition of symbol `some_task' conflicts with earlier definition at line$ +^file .* line 11: definition of symbol `some_task' conflicts with earlier definition at line 7$ ^EXIT=2$ ^SIGNAL=0$ -- -- -The line number is missing. diff --git a/src/verilog/verilog_elaborate.cpp b/src/verilog/verilog_elaborate.cpp index ab0a9de..c78ee00 100644 --- a/src/verilog/verilog_elaborate.cpp +++ b/src/verilog/verilog_elaborate.cpp @@ -523,6 +523,7 @@ void verilog_typecheckt::collect_symbols(const verilog_declt &decl) symbolt symbol{identifier, code_typet{{}, std::move(return_type)}, mode}; symbol.base_name = base_name; + symbol.location = decl.source_location(); symbol.pretty_name = strip_verilog_prefix(symbol.name); symbol.module = module_identifier; symbol.value = decl;