Verilog: add source location for function/task symbols
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@ -1,9 +1,8 @@
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KNOWNBUG
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CORE
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task_name_collision.v
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^definition of symbol `some_task' conflicts with earlier definition at line$
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^file .* line 11: definition of symbol `some_task' conflicts with earlier definition at line 7$
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^EXIT=2$
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^SIGNAL=0$
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--
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--
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The line number is missing.
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@ -523,6 +523,7 @@ void verilog_typecheckt::collect_symbols(const verilog_declt &decl)
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symbolt symbol{identifier, code_typet{{}, std::move(return_type)}, mode};
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symbol.base_name = base_name;
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symbol.location = decl.source_location();
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symbol.pretty_name = strip_verilog_prefix(symbol.name);
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symbol.module = module_identifier;
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symbol.value = decl;
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