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Verilog: add source location for function/task symbols

This commit is contained in:
Daniel Kroening 2024-02-01 13:15:54 -08:00
parent 90a19bd058
commit 2713592b1b
2 changed files with 3 additions and 3 deletions
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5
regression/verilog/tasks/task_name_collision.desc
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@ -1,9 +1,8 @@
KNOWNBUG CORE
task_name_collision.v task_name_collision.v
^definition of symbol `some_task' conflicts with earlier definition at line$ ^file .* line 11: definition of symbol `some_task' conflicts with earlier definition at line 7$
^EXIT=2$ ^EXIT=2$
^SIGNAL=0$ ^SIGNAL=0$
-- --
-- --
The line number is missing.

1
src/verilog/verilog_elaborate.cpp
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@ -523,6 +523,7 @@ void verilog_typecheckt::collect_symbols(const verilog_declt &decl)
symbolt symbol{identifier, code_typet{{}, std::move(return_type)}, mode}; symbolt symbol{identifier, code_typet{{}, std::move(return_type)}, mode};
symbol.base_name = base_name; symbol.base_name = base_name;
symbol.location = decl.source_location();
symbol.pretty_name = strip_verilog_prefix(symbol.name); symbol.pretty_name = strip_verilog_prefix(symbol.name);
symbol.module = module_identifier; symbol.module = module_identifier;
symbol.value = decl; symbol.value = decl;