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VinhTA-Computer-Master 2021-09-08 13:05:38 -07:00 committed by GitHub
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736
benchmarks/basicmath/m5out/config.ini
View File

@ -1,736 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu0 cpu1 cpu_clk_domain cpu_voltage_domain dvfs_handler mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 voltage_domain
byte_order=little
cache_line_size=64
eventq_index=0
exit_on_work_items=false
init_param=0
m5ops_base=0
mem_mode=atomic
mem_ranges=0:536870912
memories=system.mem_ctrls.dram
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
readfile=
redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2
shared_backstore=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
workload=Null
system_port=system.membus.cpu_side_ports[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu0]
type=AtomicSimpleCPU
children=dtb interrupts isa itb power_state tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu0.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
power_gating_on_idle=false
power_model=
power_state=system.cpu0.power_state
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu0.tracer
wait_for_remote_gdb=false
width=1
workload=system.cpu0.workload
dcache_port=system.membus.cpu_side_ports[2]
icache_port=system.membus.cpu_side_ports[1]
[system.cpu0.dtb]
type=ArmTLB
children=stage2_mmu walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu0.dtb.walker
[system.cpu0.dtb.stage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dtb.stage2_mmu.stage2_tlb
sys=system
tlb=system.cpu0.dtb
[system.cpu0.dtb.stage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu0.dtb.stage2_mmu.stage2_tlb.walker
[system.cpu0.dtb.stage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
children=power_state
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
power_model=
power_state=system.cpu0.dtb.stage2_mmu.stage2_tlb.walker.power_state
sys=system
[system.cpu0.dtb.stage2_mmu.stage2_tlb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[system.cpu0.dtb.walker]
type=ArmTableWalker
children=power_state
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
power_model=
power_state=system.cpu0.dtb.walker.power_state
sys=system
port=system.membus.cpu_side_ports[4]
[system.cpu0.dtb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[system.cpu0.interrupts]
type=ArmInterrupts
eventq_index=0
[system.cpu0.isa]
type=ArmISA
decoderFlavor=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=15790086
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=16846864
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=1052672
id_aa64mmfr2_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=268435456
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
impdef_nop=false
midr=0
pmu=Null
sve_vl_se=1
system=system
[system.cpu0.itb]
type=ArmTLB
children=stage2_mmu walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu0.itb.walker
[system.cpu0.itb.stage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.itb.stage2_mmu.stage2_tlb
sys=system
tlb=system.cpu0.itb
[system.cpu0.itb.stage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu0.itb.stage2_mmu.stage2_tlb.walker
[system.cpu0.itb.stage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
children=power_state
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
power_model=
power_state=system.cpu0.itb.stage2_mmu.stage2_tlb.walker.power_state
sys=system
[system.cpu0.itb.stage2_mmu.stage2_tlb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[system.cpu0.itb.walker]
type=ArmTableWalker
children=power_state
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
power_model=
power_state=system.cpu0.itb.walker.power_state
sys=system
port=system.membus.cpu_side_ports[3]
[system.cpu0.itb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[system.cpu0.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=ON CLK_GATED OFF
[system.cpu0.tracer]
type=ExeTracer
eventq_index=0
[system.cpu0.workload]
type=Process
cmd=bm_arm
cwd=/home/local/ASUAD/quoclon1/CCF_INS/ins3/benchmarks/basicmath
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=bm_arm
gid=100
input=cin
kvmInSE=false
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=0
release=5.1.0
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu1]
type=AtomicSimpleCPU
children=dtb interrupts isa itb power_state tracer
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=1
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu1.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
isa=system.cpu1.isa
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
power_gating_on_idle=false
power_model=
power_state=system.cpu1.power_state
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu1.tracer
wait_for_remote_gdb=false
width=1
workload=system.cpu0.workload
dcache_port=system.membus.cpu_side_ports[6]
icache_port=system.membus.cpu_side_ports[5]
[system.cpu1.dtb]
type=ArmTLB
children=stage2_mmu walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu1.dtb.walker
[system.cpu1.dtb.stage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dtb.stage2_mmu.stage2_tlb
sys=system
tlb=system.cpu1.dtb
[system.cpu1.dtb.stage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu1.dtb.stage2_mmu.stage2_tlb.walker
[system.cpu1.dtb.stage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
children=power_state
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
power_model=
power_state=system.cpu1.dtb.stage2_mmu.stage2_tlb.walker.power_state
sys=system
[system.cpu1.dtb.stage2_mmu.stage2_tlb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[system.cpu1.dtb.walker]
type=ArmTableWalker
children=power_state
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
power_model=
power_state=system.cpu1.dtb.walker.power_state
sys=system
port=system.membus.cpu_side_ports[8]
[system.cpu1.dtb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[system.cpu1.interrupts]
type=ArmInterrupts
eventq_index=0
[system.cpu1.isa]
type=ArmISA
decoderFlavor=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=15790086
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=16846864
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=1052672
id_aa64mmfr2_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=268435456
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
impdef_nop=false
midr=0
pmu=Null
sve_vl_se=1
system=system
[system.cpu1.itb]
type=ArmTLB
children=stage2_mmu walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu1.itb.walker
[system.cpu1.itb.stage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.itb.stage2_mmu.stage2_tlb
sys=system
tlb=system.cpu1.itb
[system.cpu1.itb.stage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu1.itb.stage2_mmu.stage2_tlb.walker
[system.cpu1.itb.stage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
children=power_state
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
power_model=
power_state=system.cpu1.itb.stage2_mmu.stage2_tlb.walker.power_state
sys=system
[system.cpu1.itb.stage2_mmu.stage2_tlb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[system.cpu1.itb.walker]
type=ArmTableWalker
children=power_state
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
power_model=
power_state=system.cpu1.itb.walker.power_state
sys=system
port=system.membus.cpu_side_ports[7]
[system.cpu1.itb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[system.cpu1.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=ON CLK_GATED OFF
[system.cpu1.tracer]
type=ExeTracer
eventq_index=0
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.cpu_voltage_domain
[system.cpu_voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.mem_ctrls]
type=MemCtrl
children=dram power_state
clk_domain=system.clk_domain
command_window=10000
dram=system.mem_ctrls.dram
eventq_index=0
mem_sched_policy=frfcfs
min_writes_per_switch=16
nvm=Null
power_model=
power_state=system.mem_ctrls.power_state
qos_policy=Null
qos_priorities=1
qos_priority_escalation=false
qos_q_policy=fifo
qos_requestors=
qos_syncro_scheduler=false
qos_turnaround_policy=Null
static_backend_latency=10000
static_frontend_latency=10000
system=system
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.mem_side_ports[0]
[system.mem_ctrls.dram]
type=DRAMInterface
children=power_state
IDD0=0.055
IDD02=0.0
IDD2N=0.032
IDD2N2=0.0
IDD2P0=0.0
IDD2P02=0.0
IDD2P1=0.032
IDD2P12=0.0
IDD3N=0.038
IDD3N2=0.0
IDD3P0=0.0
IDD3P02=0.0
IDD3P1=0.038
IDD3P12=0.0
IDD4R=0.157
IDD4R2=0.0
IDD4W=0.125
IDD4W2=0.0
IDD5=0.23500000000000001
IDD52=0.0
IDD6=0.02
IDD62=0.0
VDD=1.5
VDD2=0.0
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
beats_per_clock=2
burst_length=8
clk_domain=system.clk_domain
conf_table_reported=true
data_clock_sync=false
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
enable_dram_powerdown=false
eventq_index=0
image_file=
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
null=false
page_policy=open_adaptive
power_model=
power_state=system.mem_ctrls.dram.power_state
range=0:536870912
ranks_per_channel=2
read_buffer_size=32
tAAD=1250
tBURST=5000
tBURST_MAX=5000
tBURST_MIN=5000
tCCD_L=0
tCCD_L_WR=0
tCK=1250
tCL=13750
tCS=2500
tPPD=0
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tWTR_L=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
two_cycle_activate=false
write_buffer_size=64
[system.mem_ctrls.dram.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[system.mem_ctrls.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[system.membus]
type=CoherentXBar
children=power_state snoop_filter
clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
header_latency=1
max_outstanding_snoops=512
max_routing_table_size=512
point_of_coherency=true
point_of_unification=true
power_model=
power_state=system.membus.power_state
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
cpu_side_ports=system.system_port system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache_port system.cpu1.dcache_port system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
mem_side_ports=system.mem_ctrls.port
[system.membus.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.redirect_paths0]
type=RedirectPath
app_path=/proc
eventq_index=0
host_paths=m5out/fs/proc
[system.redirect_paths1]
type=RedirectPath
app_path=/sys
eventq_index=0
host_paths=m5out/fs/sys
[system.redirect_paths2]
type=RedirectPath
app_path=/tmp
eventq_index=0
host_paths=m5out/fs/tmp
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0

961
benchmarks/basicmath/m5out/config.json
View File

@ -1,961 +0,0 @@
{
"type": "Root",
"cxx_class": "Root",
"name": null,
"path": "root",
"eventq_index": 0,
"full_system": false,
"sim_quantum": 0,
"time_sync_enable": false,
"time_sync_period": 100000000000,
"time_sync_spin_threshold": 100000000,
"system": {
"type": "System",
"cxx_class": "System",
"name": "system",
"path": "system",
"byte_order": "little",
"cache_line_size": 64,
"eventq_index": 0,
"exit_on_work_items": false,
"init_param": 0,
"m5ops_base": 0,
"mem_mode": "atomic",
"mem_ranges": [
"0:536870912"
],
"memories": [
"system.mem_ctrls.dram"
],
"mmap_using_noreserve": false,
"multi_thread": false,
"num_work_ids": 16,
"readfile": "",
"redirect_paths": [
{
"type": "RedirectPath",
"cxx_class": "RedirectPath",
"name": "redirect_paths0",
"path": "system.redirect_paths0",
"app_path": "/proc",
"eventq_index": 0,
"host_paths": [
"m5out/fs/proc"
]
},
{
"type": "RedirectPath",
"cxx_class": "RedirectPath",
"name": "redirect_paths1",
"path": "system.redirect_paths1",
"app_path": "/sys",
"eventq_index": 0,
"host_paths": [
"m5out/fs/sys"
]
},
{
"type": "RedirectPath",
"cxx_class": "RedirectPath",
"name": "redirect_paths2",
"path": "system.redirect_paths2",
"app_path": "/tmp",
"eventq_index": 0,
"host_paths": [
"m5out/fs/tmp"
]
}
],
"shared_backstore": "",
"symbolfile": "",
"thermal_components": [],
"thermal_model": null,
"work_begin_ckpt_count": 0,
"work_begin_cpu_id_exit": -1,
"work_begin_exit_count": 0,
"work_cpus_ckpt_count": 0,
"work_end_ckpt_count": 0,
"work_end_exit_count": 0,
"work_item_id": -1,
"workload": null,
"clk_domain": {
"type": "SrcClockDomain",
"cxx_class": "SrcClockDomain",
"name": "clk_domain",
"path": "system.clk_domain",
"clock": [
1000
],
"domain_id": -1,
"eventq_index": 0,
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain"
},
"cpu": [
{
"type": "AtomicSimpleCPU",
"cxx_class": "AtomicSimpleCPU",
"name": "cpu0",
"path": "system.cpu0",
"branchPred": null,
"checker": null,
"clk_domain": "system.cpu_clk_domain",
"cpu_id": 0,
"do_checkpoint_insts": true,
"do_statistics_insts": true,
"dtb": {
"type": "ArmTLB",
"cxx_class": "ArmISA::TLB",
"name": "dtb",
"path": "system.cpu0.dtb",
"eventq_index": 0,
"is_stage2": false,
"size": 64,
"sys": "system",
"walker": {
"type": "ArmTableWalker",
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"default_state": "UNDEFINED",
"eventq_index": 0,
"leaders": [],
"possible_states": []
},
"response_latency": 2,
"snoop_filter": {
"type": "SnoopFilter",
"cxx_class": "SnoopFilter",
"name": "snoop_filter",
"path": "system.membus.snoop_filter",
"eventq_index": 0,
"lookup_latency": 1,
"max_capacity": 8388608,
"system": "system"
},
"snoop_response_latency": 4,
"system": "system",
"use_default_range": false,
"width": 16,
"cpu_side_ports": {
"role": "GEM5 RESPONDER",
"peer": [
"system.system_port",
"system.cpu0.icache_port",
"system.cpu0.dcache_port",
"system.cpu0.itb.walker.port",
"system.cpu0.dtb.walker.port",
"system.cpu1.icache_port",
"system.cpu1.dcache_port",
"system.cpu1.itb.walker.port",
"system.cpu1.dtb.walker.port"
],
"is_source": "False"
},
"mem_side_ports": {
"role": "GEM5 REQUESTOR",
"peer": [
"system.mem_ctrls.port"
],
"is_source": "True"
}
},
"voltage_domain": {
"type": "VoltageDomain",
"cxx_class": "VoltageDomain",
"name": "voltage_domain",
"path": "system.voltage_domain",
"eventq_index": 0,
"voltage": [
1.0
]
},
"system_port": {
"role": "GEM5 REQUESTOR",
"peer": "system.membus.cpu_side_ports[0]",
"is_source": "True"
}
}
}

38
benchmarks/basicmath/m5out/fs/proc/cpuinfo
View File

@ -1,38 +0,0 @@
processor : 0
vendor_id : Generic
cpu family : 0
model : 0
model name : Generic
stepping : 0
cpu MHz : 2000.000
cache size: : 2048.0K
physical id : 0
siblings : 2
core id : 0
cpu cores : 2
fpu : yes
fpu exception : yes
cpuid level : 1
wp : yes
flags : fpu
cache alignment : 64
processor : 1
vendor_id : Generic
cpu family : 0
model : 0
model name : Generic
stepping : 0
cpu MHz : 2000.000
cache size: : 2048.0K
physical id : 0
siblings : 2
core id : 1
cpu cores : 2
fpu : yes
fpu exception : yes
cpuid level : 1
wp : yes
flags : fpu
cache alignment : 64

3
benchmarks/basicmath/m5out/fs/proc/stat
View File

@ -1,3 +0,0 @@
cpu 0 0 0 0 0 0 0
cpu0 0 0 0 0 0 0 0
cpu1 0 0 0 0 0 0 0

1
benchmarks/basicmath/m5out/fs/sys/devices/system/cpu/online
View File

@ -1 +0,0 @@
0-1

1
benchmarks/basicmath/m5out/fs/sys/devices/system/cpu/possible
View File

@ -1 +0,0 @@
0-1

749
benchmarks/basicmath/m5out/stats.txt
View File

@ -1,749 +0,0 @@
---------- Begin Simulation Statistics ----------
final_tick 145521328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
host_inst_rate 1917639 # Simulator instruction rate (inst/s)
host_mem_usage 652964 # Number of bytes of host memory used
host_op_rate 2164352 # Simulator op (including micro ops) rate (op/s)
host_seconds 134.46 # Real time elapsed on the host
host_tick_rate 1082242385 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 257850966 # Number of instructions simulated
sim_ops 291024824 # Number of ops (including micro ops) simulated
sim_seconds 0.145521 # Number of seconds simulated
sim_ticks 145521328000 # Number of ticks simulated
system.cpu0.Branches 2366 # Number of branches fetched
system.cpu0.committedInsts 11413 # Number of instructions committed
system.cpu0.committedOps 13542 # Number of ops (including micro ops) committed
system.cpu0.idle_fraction 0.999953 # Percentage of idle cycles
system.cpu0.not_idle_fraction 0.000047 # Percentage of non-idle cycles
system.cpu0.numCycles 291042658 # number of cpu cycles simulated
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.num_busy_cycles 13567.000093 # Number of busy cycles
system.cpu0.num_cc_register_reads 40707 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 5742 # number of times the CC registers were written
system.cpu0.num_conditional_control_insts 1694 # number of instructions that are conditional controls
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_fp_insts 0 # number of float instructions
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu0.num_func_calls 538 # number of times a function call or return occured
system.cpu0.num_idle_cycles 291029090.999907 # Number of idle cycles
system.cpu0.num_int_alu_accesses 11797 # Number of integer alu accesses
system.cpu0.num_int_insts 11797 # number of integer instructions
system.cpu0.num_int_register_reads 19550 # number of times the integer registers were read
system.cpu0.num_int_register_writes 7457 # number of times the integer registers were written
system.cpu0.num_load_insts 2389 # Number of load instructions
system.cpu0.num_mem_refs 4804 # number of memory refs
system.cpu0.num_store_insts 2415 # Number of store instructions
system.cpu0.num_vec_alu_accesses 0 # Number of vector alu accesses
system.cpu0.num_vec_insts 0 # number of vector instructions
system.cpu0.num_vec_register_reads 16 # number of times the vector registers were read
system.cpu0.num_vec_register_writes 0 # number of times the vector registers were written
system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu 8759 64.55% 64.55% # Class of executed instruction
system.cpu0.op_class::IntMult 6 0.04% 64.60% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::FloatMultAcc 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::FloatMisc 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdDiv 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdReduceAdd 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdReduceAlu 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdReduceCmp 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatReduceAdd 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatReduceCmp 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdAes 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdAesMix 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdSha1Hash 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdSha1Hash2 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdSha256Hash 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdSha256Hash2 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdShaSigma2 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdShaSigma3 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::SimdPredAlu 0 0.00% 64.60% # Class of executed instruction
system.cpu0.op_class::MemRead 2389 17.61% 82.20% # Class of executed instruction
system.cpu0.op_class::MemWrite 2415 17.80% 100.00% # Class of executed instruction
system.cpu0.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 13569 # Class of executed instruction
system.cpu0.workload.numSyscalls 22 # Number of system calls
system.cpu1.Branches 39849115 # Number of branches fetched
system.cpu1.committedInsts 257839553 # Number of instructions committed
system.cpu1.committedOps 291011282 # Number of ops (including micro ops) committed
system.cpu1.idle_fraction 0.000046 # Percentage of idle cycles
system.cpu1.not_idle_fraction 0.999954 # Percentage of non-idle cycles
system.cpu1.numCycles 291040890 # number of cpu cycles simulated
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.num_busy_cycles 291027519.079133 # Number of busy cycles
system.cpu1.num_cc_register_reads 873194739 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 186057990 # number of times the CC registers were written
system.cpu1.num_conditional_control_insts 29575761 # number of instructions that are conditional controls
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_fp_insts 0 # number of float instructions
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu1.num_func_calls 10988299 # number of times a function call or return occured
system.cpu1.num_idle_cycles 13370.920867 # Number of idle cycles
system.cpu1.num_int_alu_accesses 262722795 # Number of integer alu accesses
system.cpu1.num_int_insts 262722795 # number of integer instructions
system.cpu1.num_int_register_reads 403684979 # number of times the integer registers were read
system.cpu1.num_int_register_writes 200248951 # number of times the integer registers were written
system.cpu1.num_load_insts 23300948 # Number of load instructions
system.cpu1.num_mem_refs 44185672 # number of memory refs
system.cpu1.num_store_insts 20884724 # Number of store instructions
system.cpu1.num_vec_alu_accesses 0 # Number of vector alu accesses
system.cpu1.num_vec_insts 0 # number of vector instructions
system.cpu1.num_vec_register_reads 16 # number of times the vector registers were read
system.cpu1.num_vec_register_writes 0 # number of times the vector registers were written
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu 242957027 83.48% 83.48% # Class of executed instruction
system.cpu1.op_class::IntMult 3758727 1.29% 84.77% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::FloatMultAcc 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::FloatMisc 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::SimdDiv 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 84.77% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 127860 0.04% 84.82% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 84.82% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.82% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.82% # Class of executed instruction
system.cpu1.op_class::SimdReduceAdd 0 0.00% 84.82% # Class of executed instruction
system.cpu1.op_class::SimdReduceAlu 0 0.00% 84.82% # Class of executed instruction
system.cpu1.op_class::SimdReduceCmp 0 0.00% 84.82% # Class of executed instruction
system.cpu1.op_class::SimdFloatReduceAdd 0 0.00% 84.82% # Class of executed instruction
system.cpu1.op_class::SimdFloatReduceCmp 0 0.00% 84.82% # Class of executed instruction
system.cpu1.op_class::SimdAes 0 0.00% 84.82% # Class of executed instruction
system.cpu1.op_class::SimdAesMix 0 0.00% 84.82% # Class of executed instruction
system.cpu1.op_class::SimdSha1Hash 0 0.00% 84.82% # Class of executed instruction
system.cpu1.op_class::SimdSha1Hash2 0 0.00% 84.82% # Class of executed instruction
system.cpu1.op_class::SimdSha256Hash 0 0.00% 84.82% # Class of executed instruction
system.cpu1.op_class::SimdSha256Hash2 0 0.00% 84.82% # Class of executed instruction
system.cpu1.op_class::SimdShaSigma2 0 0.00% 84.82% # Class of executed instruction
system.cpu1.op_class::SimdShaSigma3 0 0.00% 84.82% # Class of executed instruction
system.cpu1.op_class::SimdPredAlu 0 0.00% 84.82% # Class of executed instruction
system.cpu1.op_class::MemRead 23300948 8.01% 92.82% # Class of executed instruction
system.cpu1.op_class::MemWrite 20884724 7.18% 100.00% # Class of executed instruction
system.cpu1.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 291029286 # Class of executed instruction
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.clk_domain.clock 1000 # Clock period in ticks
system.cpu0.dtb.instHits 0 # ITB inst hits
system.cpu0.dtb.instMisses 0 # ITB inst misses
system.cpu0.dtb.readHits 0 # DTB read hits
system.cpu0.dtb.readMisses 0 # DTB read misses
system.cpu0.dtb.writeHits 0 # DTB write hits
system.cpu0.dtb.writeMisses 0 # DTB write misses
system.cpu0.dtb.inserts 0 # Number of times an entry is inserted into the TLB
system.cpu0.dtb.flushTlb 0 # Number of times complete TLB was flushed
system.cpu0.dtb.flushTlbMva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flushTlbMvaAsid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flushTlbAsid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flushedEntries 0 # Number of entries that have been flushed from TLB
system.cpu0.dtb.alignFaults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetchFaults 0 # Number of TLB faults due to prefetch
system.cpu0.dtb.domainFaults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.permsFaults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.readAccesses 0 # DTB read accesses
system.cpu0.dtb.writeAccesses 0 # DTB write accesses
system.cpu0.dtb.instAccesses 0 # ITB inst accesses
system.cpu0.dtb.hits 0 # Total TLB (inst and data) hits
system.cpu0.dtb.misses 0 # Total TLB (inst and data) misses
system.cpu0.dtb.accesses 0 # Total TLB (inst and data) accesses
system.cpu0.dtb.stage2_mmu.stage2_tlb.instHits 0 # ITB inst hits
system.cpu0.dtb.stage2_mmu.stage2_tlb.instMisses 0 # ITB inst misses
system.cpu0.dtb.stage2_mmu.stage2_tlb.readHits 0 # DTB read hits
system.cpu0.dtb.stage2_mmu.stage2_tlb.readMisses 0 # DTB read misses
system.cpu0.dtb.stage2_mmu.stage2_tlb.writeHits 0 # DTB write hits
system.cpu0.dtb.stage2_mmu.stage2_tlb.writeMisses 0 # DTB write misses
system.cpu0.dtb.stage2_mmu.stage2_tlb.inserts 0 # Number of times an entry is inserted into the TLB
system.cpu0.dtb.stage2_mmu.stage2_tlb.flushTlb 0 # Number of times complete TLB was flushed
system.cpu0.dtb.stage2_mmu.stage2_tlb.flushTlbMva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.stage2_mmu.stage2_tlb.flushTlbMvaAsid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.stage2_mmu.stage2_tlb.flushTlbAsid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.stage2_mmu.stage2_tlb.flushedEntries 0 # Number of entries that have been flushed from TLB
system.cpu0.dtb.stage2_mmu.stage2_tlb.alignFaults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.stage2_mmu.stage2_tlb.prefetchFaults 0 # Number of TLB faults due to prefetch
system.cpu0.dtb.stage2_mmu.stage2_tlb.domainFaults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.stage2_mmu.stage2_tlb.permsFaults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.stage2_mmu.stage2_tlb.readAccesses 0 # DTB read accesses
system.cpu0.dtb.stage2_mmu.stage2_tlb.writeAccesses 0 # DTB write accesses
system.cpu0.dtb.stage2_mmu.stage2_tlb.instAccesses 0 # ITB inst accesses
system.cpu0.dtb.stage2_mmu.stage2_tlb.hits 0 # Total TLB (inst and data) hits
system.cpu0.dtb.stage2_mmu.stage2_tlb.misses 0 # Total TLB (inst and data) misses
system.cpu0.dtb.stage2_mmu.stage2_tlb.accesses 0 # Total TLB (inst and data) accesses
system.cpu0.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 145521328000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 0 # Table walker walks requested
system.cpu0.dtb.walker.requestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.requestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.requestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.requestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.requestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.requestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.requestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 145521328000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.instHits 0 # ITB inst hits
system.cpu0.itb.instMisses 0 # ITB inst misses
system.cpu0.itb.readHits 0 # DTB read hits
system.cpu0.itb.readMisses 0 # DTB read misses
system.cpu0.itb.writeHits 0 # DTB write hits
system.cpu0.itb.writeMisses 0 # DTB write misses
system.cpu0.itb.inserts 0 # Number of times an entry is inserted into the TLB
system.cpu0.itb.flushTlb 0 # Number of times complete TLB was flushed
system.cpu0.itb.flushTlbMva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flushTlbMvaAsid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flushTlbAsid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.flushedEntries 0 # Number of entries that have been flushed from TLB
system.cpu0.itb.alignFaults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetchFaults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domainFaults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.permsFaults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.readAccesses 0 # DTB read accesses
system.cpu0.itb.writeAccesses 0 # DTB write accesses
system.cpu0.itb.instAccesses 0 # ITB inst accesses
system.cpu0.itb.hits 0 # Total TLB (inst and data) hits
system.cpu0.itb.misses 0 # Total TLB (inst and data) misses
system.cpu0.itb.accesses 0 # Total TLB (inst and data) accesses
system.cpu0.itb.stage2_mmu.stage2_tlb.instHits 0 # ITB inst hits
system.cpu0.itb.stage2_mmu.stage2_tlb.instMisses 0 # ITB inst misses
system.cpu0.itb.stage2_mmu.stage2_tlb.readHits 0 # DTB read hits
system.cpu0.itb.stage2_mmu.stage2_tlb.readMisses 0 # DTB read misses
system.cpu0.itb.stage2_mmu.stage2_tlb.writeHits 0 # DTB write hits
system.cpu0.itb.stage2_mmu.stage2_tlb.writeMisses 0 # DTB write misses
system.cpu0.itb.stage2_mmu.stage2_tlb.inserts 0 # Number of times an entry is inserted into the TLB
system.cpu0.itb.stage2_mmu.stage2_tlb.flushTlb 0 # Number of times complete TLB was flushed
system.cpu0.itb.stage2_mmu.stage2_tlb.flushTlbMva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.stage2_mmu.stage2_tlb.flushTlbMvaAsid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.stage2_mmu.stage2_tlb.flushTlbAsid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.stage2_mmu.stage2_tlb.flushedEntries 0 # Number of entries that have been flushed from TLB
system.cpu0.itb.stage2_mmu.stage2_tlb.alignFaults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.stage2_mmu.stage2_tlb.prefetchFaults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.stage2_mmu.stage2_tlb.domainFaults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.stage2_mmu.stage2_tlb.permsFaults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.stage2_mmu.stage2_tlb.readAccesses 0 # DTB read accesses
system.cpu0.itb.stage2_mmu.stage2_tlb.writeAccesses 0 # DTB write accesses
system.cpu0.itb.stage2_mmu.stage2_tlb.instAccesses 0 # ITB inst accesses
system.cpu0.itb.stage2_mmu.stage2_tlb.hits 0 # Total TLB (inst and data) hits
system.cpu0.itb.stage2_mmu.stage2_tlb.misses 0 # Total TLB (inst and data) misses
system.cpu0.itb.stage2_mmu.stage2_tlb.accesses 0 # Total TLB (inst and data) accesses
system.cpu0.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.stage2_mmu.stage2_tlb.walker.requestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 145521328000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 0 # Table walker walks requested
system.cpu0.itb.walker.requestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.requestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.requestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.requestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.requestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.requestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.requestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 145521328000 # Cumulative time (in ticks) in various power states
system.cpu0.power_state.numTransitions 2 # Number of power state transitions
system.cpu0.power_state.ticksClkGated::samples 1 # Distribution of time spent in the clock gated state
system.cpu0.power_state.ticksClkGated::mean 145514544500 # Distribution of time spent in the clock gated state
system.cpu0.power_state.ticksClkGated::1e+11-1.5e+11 1 100.00% 100.00% # Distribution of time spent in the clock gated state
system.cpu0.power_state.ticksClkGated::min_value 145514544500 # Distribution of time spent in the clock gated state
system.cpu0.power_state.ticksClkGated::max_value 145514544500 # Distribution of time spent in the clock gated state
system.cpu0.power_state.ticksClkGated::total 1 # Distribution of time spent in the clock gated state
system.cpu0.power_state.pwrStateResidencyTicks::ON 6783500 # Cumulative time (in ticks) in various power states
system.cpu0.power_state.pwrStateResidencyTicks::CLK_GATED 145514544500 # Cumulative time (in ticks) in various power states
system.cpu0.thread_0.numInsts 0 # Number of Instructions committed
system.cpu0.thread_0.numOps 0 # Number of Ops committed
system.cpu0.thread_0.numMemRefs 0 # Number of Memory References
system.cpu1.dtb.instHits 0 # ITB inst hits
system.cpu1.dtb.instMisses 0 # ITB inst misses
system.cpu1.dtb.readHits 0 # DTB read hits
system.cpu1.dtb.readMisses 0 # DTB read misses
system.cpu1.dtb.writeHits 0 # DTB write hits
system.cpu1.dtb.writeMisses 0 # DTB write misses
system.cpu1.dtb.inserts 0 # Number of times an entry is inserted into the TLB
system.cpu1.dtb.flushTlb 0 # Number of times complete TLB was flushed
system.cpu1.dtb.flushTlbMva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flushTlbMvaAsid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flushTlbAsid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flushedEntries 0 # Number of entries that have been flushed from TLB
system.cpu1.dtb.alignFaults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetchFaults 0 # Number of TLB faults due to prefetch
system.cpu1.dtb.domainFaults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.permsFaults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.readAccesses 0 # DTB read accesses
system.cpu1.dtb.writeAccesses 0 # DTB write accesses
system.cpu1.dtb.instAccesses 0 # ITB inst accesses
system.cpu1.dtb.hits 0 # Total TLB (inst and data) hits
system.cpu1.dtb.misses 0 # Total TLB (inst and data) misses
system.cpu1.dtb.accesses 0 # Total TLB (inst and data) accesses
system.cpu1.dtb.stage2_mmu.stage2_tlb.instHits 0 # ITB inst hits
system.cpu1.dtb.stage2_mmu.stage2_tlb.instMisses 0 # ITB inst misses
system.cpu1.dtb.stage2_mmu.stage2_tlb.readHits 0 # DTB read hits
system.cpu1.dtb.stage2_mmu.stage2_tlb.readMisses 0 # DTB read misses
system.cpu1.dtb.stage2_mmu.stage2_tlb.writeHits 0 # DTB write hits
system.cpu1.dtb.stage2_mmu.stage2_tlb.writeMisses 0 # DTB write misses
system.cpu1.dtb.stage2_mmu.stage2_tlb.inserts 0 # Number of times an entry is inserted into the TLB
system.cpu1.dtb.stage2_mmu.stage2_tlb.flushTlb 0 # Number of times complete TLB was flushed
system.cpu1.dtb.stage2_mmu.stage2_tlb.flushTlbMva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.stage2_mmu.stage2_tlb.flushTlbMvaAsid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.stage2_mmu.stage2_tlb.flushTlbAsid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.stage2_mmu.stage2_tlb.flushedEntries 0 # Number of entries that have been flushed from TLB
system.cpu1.dtb.stage2_mmu.stage2_tlb.alignFaults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.stage2_mmu.stage2_tlb.prefetchFaults 0 # Number of TLB faults due to prefetch
system.cpu1.dtb.stage2_mmu.stage2_tlb.domainFaults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.stage2_mmu.stage2_tlb.permsFaults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.stage2_mmu.stage2_tlb.readAccesses 0 # DTB read accesses
system.cpu1.dtb.stage2_mmu.stage2_tlb.writeAccesses 0 # DTB write accesses
system.cpu1.dtb.stage2_mmu.stage2_tlb.instAccesses 0 # ITB inst accesses
system.cpu1.dtb.stage2_mmu.stage2_tlb.hits 0 # Total TLB (inst and data) hits
system.cpu1.dtb.stage2_mmu.stage2_tlb.misses 0 # Total TLB (inst and data) misses
system.cpu1.dtb.stage2_mmu.stage2_tlb.accesses 0 # Total TLB (inst and data) accesses
system.cpu1.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.stage2_mmu.stage2_tlb.walker.requestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 145521328000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 0 # Table walker walks requested
system.cpu1.dtb.walker.requestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.requestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.requestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.requestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.requestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.requestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.requestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 145521328000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.instHits 0 # ITB inst hits
system.cpu1.itb.instMisses 0 # ITB inst misses
system.cpu1.itb.readHits 0 # DTB read hits
system.cpu1.itb.readMisses 0 # DTB read misses
system.cpu1.itb.writeHits 0 # DTB write hits
system.cpu1.itb.writeMisses 0 # DTB write misses
system.cpu1.itb.inserts 0 # Number of times an entry is inserted into the TLB
system.cpu1.itb.flushTlb 0 # Number of times complete TLB was flushed
system.cpu1.itb.flushTlbMva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flushTlbMvaAsid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flushTlbAsid 0 # Number of times TLB was flushed by ASID
system.cpu1.itb.flushedEntries 0 # Number of entries that have been flushed from TLB
system.cpu1.itb.alignFaults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetchFaults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domainFaults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.permsFaults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.readAccesses 0 # DTB read accesses
system.cpu1.itb.writeAccesses 0 # DTB write accesses
system.cpu1.itb.instAccesses 0 # ITB inst accesses
system.cpu1.itb.hits 0 # Total TLB (inst and data) hits
system.cpu1.itb.misses 0 # Total TLB (inst and data) misses
system.cpu1.itb.accesses 0 # Total TLB (inst and data) accesses
system.cpu1.itb.stage2_mmu.stage2_tlb.instHits 0 # ITB inst hits
system.cpu1.itb.stage2_mmu.stage2_tlb.instMisses 0 # ITB inst misses
system.cpu1.itb.stage2_mmu.stage2_tlb.readHits 0 # DTB read hits
system.cpu1.itb.stage2_mmu.stage2_tlb.readMisses 0 # DTB read misses
system.cpu1.itb.stage2_mmu.stage2_tlb.writeHits 0 # DTB write hits
system.cpu1.itb.stage2_mmu.stage2_tlb.writeMisses 0 # DTB write misses
system.cpu1.itb.stage2_mmu.stage2_tlb.inserts 0 # Number of times an entry is inserted into the TLB
system.cpu1.itb.stage2_mmu.stage2_tlb.flushTlb 0 # Number of times complete TLB was flushed
system.cpu1.itb.stage2_mmu.stage2_tlb.flushTlbMva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.stage2_mmu.stage2_tlb.flushTlbMvaAsid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.stage2_mmu.stage2_tlb.flushTlbAsid 0 # Number of times TLB was flushed by ASID
system.cpu1.itb.stage2_mmu.stage2_tlb.flushedEntries 0 # Number of entries that have been flushed from TLB
system.cpu1.itb.stage2_mmu.stage2_tlb.alignFaults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.stage2_mmu.stage2_tlb.prefetchFaults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.stage2_mmu.stage2_tlb.domainFaults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.stage2_mmu.stage2_tlb.permsFaults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.stage2_mmu.stage2_tlb.readAccesses 0 # DTB read accesses
system.cpu1.itb.stage2_mmu.stage2_tlb.writeAccesses 0 # DTB write accesses
system.cpu1.itb.stage2_mmu.stage2_tlb.instAccesses 0 # ITB inst accesses
system.cpu1.itb.stage2_mmu.stage2_tlb.hits 0 # Total TLB (inst and data) hits
system.cpu1.itb.stage2_mmu.stage2_tlb.misses 0 # Total TLB (inst and data) misses
system.cpu1.itb.stage2_mmu.stage2_tlb.accesses 0 # Total TLB (inst and data) accesses
system.cpu1.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.stage2_mmu.stage2_tlb.walker.requestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.stage2_mmu.stage2_tlb.walker.requestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 145521328000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 0 # Table walker walks requested
system.cpu1.itb.walker.requestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.requestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.requestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.requestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.requestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.requestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.requestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 145521328000 # Cumulative time (in ticks) in various power states
system.cpu1.power_state.pwrStateResidencyTicks::ON 145521328000 # Cumulative time (in ticks) in various power states
system.cpu1.thread_0.numInsts 0 # Number of Instructions committed
system.cpu1.thread_0.numOps 0 # Number of Ops committed
system.cpu1.thread_0.numMemRefs 0 # Number of Memory References
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu_voltage_domain.voltage 1 # Voltage in Volts
system.mem_ctrls.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (s)
system.mem_ctrls.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (s)
system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE
system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ
system.mem_ctrls.numStayReadState 0 # Number of times bus staying in READ state
system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state
system.mem_ctrls.readReqs 0 # Number of read requests accepted
system.mem_ctrls.writeReqs 0 # Number of write requests accepted
system.mem_ctrls.readBursts 0 # Number of controller read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 0 # Number of controller write bursts, including those merged in the write queue
system.mem_ctrls.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 0 # Number of controller write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrls.avgRdQLen 0.00 # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 0 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue
system.mem_ctrls.bytesReadSys 0 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side
system.mem_ctrls.avgRdBWSys 0.00 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.mem_ctrls.totGap 0 # Total gap between requests
system.mem_ctrls.avgGap nan # Average gap between requests
system.mem_ctrls.dram.bytes_read::.cpu0.inst 45760 # Number of bytes read from this memory
system.mem_ctrls.dram.bytes_read::.cpu0.data 10594 # Number of bytes read from this memory
system.mem_ctrls.dram.bytes_read::.cpu1.inst 1031430228 # Number of bytes read from this memory
system.mem_ctrls.dram.bytes_read::.cpu1.data 111382439 # Number of bytes read from this memory
system.mem_ctrls.dram.bytes_read::total 1142869021 # Number of bytes read from this memory
system.mem_ctrls.dram.bytes_inst_read::.cpu0.inst 45760 # Number of instructions bytes read from this memory
system.mem_ctrls.dram.bytes_inst_read::.cpu1.inst 1031430228 # Number of instructions bytes read from this memory
system.mem_ctrls.dram.bytes_inst_read::total 1031475988 # Number of instructions bytes read from this memory
system.mem_ctrls.dram.bytes_written::.cpu0.data 8970 # Number of bytes written to this memory
system.mem_ctrls.dram.bytes_written::.cpu1.data 79309276 # Number of bytes written to this memory
system.mem_ctrls.dram.bytes_written::total 79318246 # Number of bytes written to this memory
system.mem_ctrls.dram.num_reads::.cpu0.inst 11440 # Number of read requests responded to by this memory
system.mem_ctrls.dram.num_reads::.cpu0.data 2317 # Number of read requests responded to by this memory
system.mem_ctrls.dram.num_reads::.cpu1.inst 257857557 # Number of read requests responded to by this memory
system.mem_ctrls.dram.num_reads::.cpu1.data 20850150 # Number of read requests responded to by this memory
system.mem_ctrls.dram.num_reads::total 278721464 # Number of read requests responded to by this memory
system.mem_ctrls.dram.num_writes::.cpu0.data 2306 # Number of write requests responded to by this memory
system.mem_ctrls.dram.num_writes::.cpu1.data 20136361 # Number of write requests responded to by this memory
system.mem_ctrls.dram.num_writes::total 20138667 # Number of write requests responded to by this memory
system.mem_ctrls.dram.bw_read::.cpu0.inst 314456 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_read::.cpu0.data 72800 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_read::.cpu1.inst 7087828583 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_read::.cpu1.data 765402849 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_read::total 7853618687 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_inst_read::.cpu0.inst 314456 # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_inst_read::.cpu1.inst 7087828583 # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_inst_read::total 7088143038 # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_write::.cpu0.data 61640 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_write::.cpu1.data 545001046 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_write::total 545062687 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.dram.bw_total::.cpu0.inst 314456 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.dram.bw_total::.cpu0.data 134441 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.dram.bw_total::.cpu1.inst 7087828583 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.dram.bw_total::.cpu1.data 1310403895 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.dram.bw_total::total 8398681374 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.dram.readBursts 0 # Number of DRAM read bursts
system.mem_ctrls.dram.writeBursts 0 # Number of DRAM write bursts
system.mem_ctrls.dram.perBankRdBursts::0 0 # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::1 0 # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::2 0 # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::3 0 # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::4 0 # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::5 0 # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::6 0 # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::7 0 # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::8 0 # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::9 0 # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::10 0 # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::11 0 # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::12 0 # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::13 0 # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::14 0 # Per bank write bursts
system.mem_ctrls.dram.perBankRdBursts::15 0 # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::2 0 # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::3 0 # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::4 0 # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::5 0 # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::6 0 # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::7 0 # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::8 0 # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::9 0 # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::10 0 # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::11 0 # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::12 0 # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::13 0 # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::14 0 # Per bank write bursts
system.mem_ctrls.dram.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.dram.totQLat 0 # Total ticks spent queuing
system.mem_ctrls.dram.totBusLat 0 # Total ticks spent in databus transfers
system.mem_ctrls.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.dram.avgQLat nan # Average queueing delay per DRAM burst
system.mem_ctrls.dram.avgBusLat nan # Average bus latency per DRAM burst
system.mem_ctrls.dram.avgMemAccLat nan # Average memory access latency per DRAM burst
system.mem_ctrls.dram.readRowHits 0 # Number of row buffer hits during reads
system.mem_ctrls.dram.writeRowHits 0 # Number of row buffer hits during writes
system.mem_ctrls.dram.readRowHitRate nan # Row buffer hit rate for reads
system.mem_ctrls.dram.writeRowHitRate nan # Row buffer hit rate for writes
system.mem_ctrls.dram.bytesRead 0 # Total number of bytes read from DRAM
system.mem_ctrls.dram.bytesWritten 0 # Total number of bytes written to DRAM
system.mem_ctrls.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s
system.mem_ctrls.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s
system.mem_ctrls.dram.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.dram.busUtil 0.00 # Data bus utilization in percentage
system.mem_ctrls.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads
system.mem_ctrls.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.mem_ctrls.dram.pageHitRate nan # Row buffer hit rate, read and write combined
system.mem_ctrls.dram.power_state.pwrStateResidencyTicks::UNDEFINED 145521328000 # Cumulative time (in ticks) in various power states
system.mem_ctrls.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ)
system.mem_ctrls.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ)
system.mem_ctrls.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ)
system.mem_ctrls.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.mem_ctrls.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ)
system.mem_ctrls.dram.rank0.actBackEnergy 0 # Energy for active background per rank (pJ)
system.mem_ctrls.dram.rank0.preBackEnergy 55880190240 # Energy for precharge background per rank (pJ)
system.mem_ctrls.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ)
system.mem_ctrls.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ)
system.mem_ctrls.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
system.mem_ctrls.dram.rank0.totalEnergy 55880190240 # Total energy per rank (pJ)
system.mem_ctrls.dram.rank0.averagePower 384.000002 # Core power per rank (mW)
system.mem_ctrls.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank
system.mem_ctrls.dram.rank0.pwrStateTime::IDLE 145521328000 # Time in different power states
system.mem_ctrls.dram.rank0.pwrStateTime::REF 0 # Time in different power states
system.mem_ctrls.dram.rank0.pwrStateTime::SREF 0 # Time in different power states
system.mem_ctrls.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls.dram.rank0.pwrStateTime::ACT 0 # Time in different power states
system.mem_ctrls.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ)
system.mem_ctrls.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ)
system.mem_ctrls.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ)
system.mem_ctrls.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.mem_ctrls.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ)
system.mem_ctrls.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ)
system.mem_ctrls.dram.rank1.preBackEnergy 55880190240 # Energy for precharge background per rank (pJ)
system.mem_ctrls.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ)
system.mem_ctrls.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ)
system.mem_ctrls.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
system.mem_ctrls.dram.rank1.totalEnergy 55880190240 # Total energy per rank (pJ)
system.mem_ctrls.dram.rank1.averagePower 384.000002 # Core power per rank (mW)
system.mem_ctrls.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank
system.mem_ctrls.dram.rank1.pwrStateTime::IDLE 145521328000 # Time in different power states
system.mem_ctrls.dram.rank1.pwrStateTime::REF 0 # Time in different power states
system.mem_ctrls.dram.rank1.pwrStateTime::SREF 0 # Time in different power states
system.mem_ctrls.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls.dram.rank1.pwrStateTime::ACT 0 # Time in different power states
system.mem_ctrls.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 145521328000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 278609445 # Transaction distribution
system.membus.trans_dist::ReadResp 278721464 # Transaction distribution
system.membus.trans_dist::WriteReq 20026648 # Transaction distribution
system.membus.trans_dist::WriteResp 20026648 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 112019 # Transaction distribution
system.membus.trans_dist::StoreCondReq 112019 # Transaction distribution
system.membus.trans_dist::StoreCondResp 112019 # Transaction distribution
system.membus.pkt_count_system.cpu0.icache_port::system.mem_ctrls.port 22880 # Packet count per connected requestor and responder (bytes)
system.membus.pkt_count_system.cpu0.dcache_port::system.mem_ctrls.port 9246 # Packet count per connected requestor and responder (bytes)
system.membus.pkt_count_system.cpu1.icache_port::system.mem_ctrls.port 515715114 # Packet count per connected requestor and responder (bytes)
system.membus.pkt_count_system.cpu1.dcache_port::system.mem_ctrls.port 81973022 # Packet count per connected requestor and responder (bytes)
system.membus.pkt_count::total 597720262 # Packet count per connected requestor and responder (bytes)
system.membus.pkt_size_system.cpu0.icache_port::system.mem_ctrls.port 45760 # Cumulative packet size per connected requestor and responder (bytes)
system.membus.pkt_size_system.cpu0.dcache_port::system.mem_ctrls.port 19564 # Cumulative packet size per connected requestor and responder (bytes)
system.membus.pkt_size_system.cpu1.icache_port::system.mem_ctrls.port 1031430228 # Cumulative packet size per connected requestor and responder (bytes)
system.membus.pkt_size_system.cpu1.dcache_port::system.mem_ctrls.port 190691715 # Cumulative packet size per connected requestor and responder (bytes)
system.membus.pkt_size::total 1222187267 # Cumulative packet size per connected requestor and responder (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 298860131 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 298860131 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 298860131 # Request fanout histogram
system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 145521328000 # Cumulative time (in ticks) in various power states
system.voltage_domain.voltage 1 # Voltage in Volts
---------- End Simulation Statistics ----------