24 lines
1.1 KiB
Tcl
24 lines
1.1 KiB
Tcl
########################################################################################################
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# USER LAYER SYNTHESIS
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########################################################################################################
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puts "[color $clr_flow "** Starting user layer synthesis ..."]"
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puts "[color $clr_flow "**"]"
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for {set i 0} {$i < $cfg(n_config)} {incr i} {
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for {set j 0} {$j < $cfg(n_reg)} {incr j} {
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open_project "$build_dir/$project\_config_$i/user\_c$i\_$j/$project.xpr"
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update_compile_order
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#set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-mode out_of_context} -objects [get_runs synth_1]
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reset_run synth_1
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launch_runs -jobs $cfg(cores) -verbose synth_1
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wait_on_run synth_1
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open_run synth_1
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write_checkpoint -force "$dcp_dir/config_$i/user_synthed_c$i\_$j.dcp"
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report_utilization -file "$rprt_dir/config_$i/user_synthed_c$i\_$j.rpt"
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close_project
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puts "[color $clr_flow "** vFPGA_C$i\_$j synthesized"]"
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puts "[color $clr_flow "**"]"
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}
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} |