241 lines
15 KiB
Tcl
241 lines
15 KiB
Tcl
#
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# Clocks
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#
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# Clock gen
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set cmd "set clk_wiz_shell \[ create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name clk_wiz_shell ]"
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eval $cmd
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set cmd "set_property -dict \[list \
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CONFIG.USE_PHASE_ALIGNMENT {true} \
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CONFIG.USE_PHASE_ALIGNMENT {true} \
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CONFIG.PRIM_SOURCE {Single_ended_clock_capable_pin} \
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CONFIG.PRIM_IN_FREQ {250.000} \
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CONFIG.CLKOUT2_USED {true} \
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CONFIG.CLKOUT3_USED {true} \
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CONFIG.CLKOUT4_USED {true} \
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CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {[expr {$cfg(aclk_f)}]} \
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CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {[expr {$cfg(nclk_f)}]} \
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CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {[expr {$cfg(uclk_f)}]} \
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CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {300} \
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CONFIG.SECONDARY_SOURCE {Single_ended_clock_capable_pin} \
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CONFIG.CLKOUT1_DRIVES {Buffer} \
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CONFIG.CLKOUT2_DRIVES {Buffer} \
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CONFIG.CLKOUT3_DRIVES {Buffer} \
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CONFIG.CLKOUT4_DRIVES {Buffer} \
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CONFIG.NUM_OUT_CLKS {3} \
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CONFIG.CLKOUT1_JITTER {102.086} \
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CONFIG.CLKOUT2_JITTER {94.862} \
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CONFIG.CLKOUT2_PHASE_ERROR {87.180} \
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CONFIG.CLKOUT3_JITTER {94.862} \
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CONFIG.CLKOUT3_PHASE_ERROR {87.180} \
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CONFIG.USE_LOCKED {false} \
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CONFIG.USE_RESET {false} \
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] \[get_ips clk_wiz_shell]"
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eval $cmd
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# Reset sync
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create_ip -name proc_sys_reset -vendor xilinx.com -library ip -version 5.0 -module_name proc_sys_reset_a;
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set_property -dict [list CONFIG.C_EXT_RESET_HIGH {1}] [get_ips proc_sys_reset_a]
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create_ip -name proc_sys_reset -vendor xilinx.com -library ip -version 5.0 -module_name proc_sys_reset_n;
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set_property -dict [list CONFIG.C_EXT_RESET_HIGH {1}] [get_ips proc_sys_reset_n]
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create_ip -name proc_sys_reset -vendor xilinx.com -library ip -version 5.0 -module_name proc_sys_reset_u;
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set_property -dict [list CONFIG.C_EXT_RESET_HIGH {1}] [get_ips proc_sys_reset_u]
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#
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# Register slices
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#
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# Split
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create_ip -name axi_register_slice -vendor xilinx.com -library ip -version 2.1 -module_name axi_reg_shell_src_s0_int
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set_property -dict [list CONFIG.ADDR_WIDTH {64} CONFIG.DATA_WIDTH {512} CONFIG.ID_WIDTH {6} CONFIG.REG_AW {0} CONFIG.REG_AR {0} CONFIG.REG_R {0} CONFIG.REG_B {0} ] [get_ips axi_reg_shell_src_s0_int]
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create_ip -name axi_register_slice -vendor xilinx.com -library ip -version 2.1 -module_name axi_reg_shell_src_s2_int
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set_property -dict [list CONFIG.ADDR_WIDTH {64} CONFIG.DATA_WIDTH {64} ] [get_ips axi_reg_shell_src_s2_int]
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create_ip -name axi_register_slice -vendor xilinx.com -library ip -version 2.1 -module_name axi_reg_shell_src_s4_int
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set_property -dict [list CONFIG.ADDR_WIDTH {64} CONFIG.DATA_WIDTH {64} CONFIG.REG_W {7} CONFIG.REG_R {7} CONFIG.PROTOCOL {AXI4LITE}] [get_ips axi_reg_shell_src_s4_int]
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create_ip -name axi_register_slice -vendor xilinx.com -library ip -version 2.1 -module_name axim_reg_shell_src_s0_int
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set_property -dict [list CONFIG.ADDR_WIDTH {64} CONFIG.DATA_WIDTH {512} CONFIG.ID_WIDTH {6} CONFIG.REG_AW {0} CONFIG.REG_AR {0} CONFIG.REG_R {0} CONFIG.REG_B {0} ] [get_ips axim_reg_shell_src_s0_int]
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create_ip -name axi_register_slice -vendor xilinx.com -library ip -version 2.1 -module_name axim_reg_shell_src_s2_int
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set_property -dict [list CONFIG.ADDR_WIDTH {64} CONFIG.DATA_WIDTH {256} ] [get_ips axim_reg_shell_src_s2_int]
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create_ip -name axi_register_slice -vendor xilinx.com -library ip -version 2.1 -module_name axi_reg_shell_sink_int
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set_property -dict [list CONFIG.ADDR_WIDTH {64} CONFIG.DATA_WIDTH {512} CONFIG.ID_WIDTH {6} ] [get_ips axi_reg_shell_sink_int]
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# HBM
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create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_hbm_r
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set_property -dict [list CONFIG.TDATA_NUM_BYTES {64} CONFIG.TUSER_WIDTH {4} CONFIG.FIFO_DEPTH {128} CONFIG.HAS_TLAST {1} ] [get_ips axis_data_fifo_hbm_r]
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create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_hbm_w
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set_property -dict [list CONFIG.TDATA_NUM_BYTES {64} CONFIG.FIFO_DEPTH {128} CONFIG.HAS_TSTRB {1} CONFIG.HAS_TLAST {1} ] [get_ips axis_data_fifo_hbm_w]
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create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_hbm_b
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set_property -dict [list CONFIG.TDATA_NUM_BYTES {0} CONFIG.TUSER_WIDTH {4} CONFIG.FIFO_DEPTH {128} ] [get_ips axis_data_fifo_hbm_b]
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# Split
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create_ip -name axi_data_fifo -vendor xilinx.com -library ip -version 2.1 -module_name axi_data_fifo_shell_sink_int
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set_property -dict [list CONFIG.ADDR_WIDTH {64} CONFIG.DATA_WIDTH {512} CONFIG.ID_WIDTH {6} CONFIG.WRITE_FIFO_DEPTH {512} CONFIG.READ_FIFO_DEPTH {512} CONFIG.WRITE_FIFO_DELAY {1} CONFIG.READ_FIFO_DELAY {1}] [get_ips axi_data_fifo_shell_sink_int]
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#
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# Dwidth
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#
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create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name axi_dwidth_shell_src_s1_int
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set_property -dict [list CONFIG.ADDR_WIDTH {64} CONFIG.SI_DATA_WIDTH {512} CONFIG.SI_ID_WIDTH {6} CONFIG.MI_DATA_WIDTH {64}] [get_ips axi_dwidth_shell_src_s1_int]
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create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name axim_dwidth_shell_src_s1_int
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set_property -dict [list CONFIG.ADDR_WIDTH {64} CONFIG.SI_DATA_WIDTH {512} CONFIG.MI_DATA_WIDTH {256} CONFIG.SI_ID_WIDTH {6}] [get_ips axim_dwidth_shell_src_s1_int]
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#
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# Protocols
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#
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create_ip -name axi_protocol_converter -vendor xilinx.com -library ip -version 2.1 -module_name axi_protocol_shell_src_s3_int
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set_property -dict [list CONFIG.ADDR_WIDTH {64} CONFIG.DATA_WIDTH {64}] [get_ips axi_protocol_shell_src_s3_int]
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#
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# XBARs
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#
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create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module_name shell_xbar
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set cmd [format "set_property -dict \[list \
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CONFIG.ID_WIDTH {4} \
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CONFIG.ADDR_WIDTH {64} \
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CONFIG.DATA_WIDTH {512} \
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CONFIG.S00_WRITE_ACCEPTANCE {8} \
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CONFIG.S00_READ_ACCEPTANCE {8} \
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CONFIG.S00_THREAD_ID_WIDTH {4} \
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CONFIG.S01_THREAD_ID_WIDTH {4} \
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CONFIG.S02_THREAD_ID_WIDTH {4} \
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CONFIG.S03_THREAD_ID_WIDTH {4} \
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CONFIG.S04_THREAD_ID_WIDTH {4} \
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CONFIG.S05_THREAD_ID_WIDTH {4} \
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CONFIG.S06_THREAD_ID_WIDTH {4} \
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CONFIG.S07_THREAD_ID_WIDTH {4} \
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CONFIG.S08_THREAD_ID_WIDTH {4} \
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CONFIG.S09_THREAD_ID_WIDTH {4} \
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CONFIG.S10_THREAD_ID_WIDTH {4} \
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CONFIG.S11_THREAD_ID_WIDTH {4} \
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CONFIG.S12_THREAD_ID_WIDTH {4} \
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CONFIG.S13_THREAD_ID_WIDTH {4} \
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CONFIG.S14_THREAD_ID_WIDTH {4} \
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CONFIG.S15_THREAD_ID_WIDTH {4} \
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CONFIG.S01_BASE_ID {0x00000010} \
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CONFIG.S02_BASE_ID {0x00000020} \
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CONFIG.S03_BASE_ID {0x00000030} \
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CONFIG.S04_BASE_ID {0x00000040} \
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CONFIG.S05_BASE_ID {0x00000050} \
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CONFIG.S06_BASE_ID {0x00000060} \
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CONFIG.S07_BASE_ID {0x00000070} \
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CONFIG.S08_BASE_ID {0x00000080} \
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CONFIG.S09_BASE_ID {0x00000090} \
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CONFIG.S10_BASE_ID {0x000000a0} \
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CONFIG.S11_BASE_ID {0x000000b0} \
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CONFIG.S12_BASE_ID {0x000000c0} \
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CONFIG.S13_BASE_ID {0x000000d0} \
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CONFIG.S14_BASE_ID {0x000000e0} \
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CONFIG.S15_BASE_ID {0x000000f0} \
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CONFIG.M00_WRITE_ISSUING {8} \
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CONFIG.M00_READ_ISSUING {8} \
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CONFIG.M00_A00_BASE_ADDR {0x0000000000000000} \
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CONFIG.M00_A00_ADDR_WIDTH {15} "]
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if {$cfg(en_avx) eq 1} {
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append cmd "CONFIG.NUM_MI {[expr {2* $cfg(n_reg) + 1}]} "
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for {set i 0} {$i < $cfg(n_reg)} {incr i} {
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append cmd [format "CONFIG.M%02d_WRITE_ISSUING {8} " [expr {2*$i+1}]]
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append cmd [format "CONFIG.M%02d_WRITE_ISSUING {8} " [expr {2*$i+2}]]
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append cmd [format "CONFIG.M%02d_READ_ISSUING {8} " [expr {2*$i+1}]]
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append cmd [format "CONFIG.M%02d_READ_ISSUING {8} " [expr {2*$i+2}]]
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append cmd [format "CONFIG.M%02d_A00_ADDR_WIDTH {18} " [expr {2*$i+1}]]
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append cmd [format "CONFIG.M%02d_A00_ADDR_WIDTH {18} " [expr {2*$i+2}]]
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append cmd [format "CONFIG.M%02d_A00_BASE_ADDR {0x0000000000%02x0000} " [expr {2*$i+1}] [expr {0x10 + $i*4}]]
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append cmd [format "CONFIG.M%02d_A00_BASE_ADDR {0x000000000%03x0000} " [expr {2*$i+2}] [expr {0x100 + $i*4}]]
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}
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} else {
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append cmd "CONFIG.NUM_MI {[expr {$cfg(n_reg) + 1}]} "
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for {set i 0} {$i < $cfg(n_reg)} {incr i} {
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append cmd [format "CONFIG.M%02d_WRITE_ISSUING {8} " [expr {$i+1}]]
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append cmd [format "CONFIG.M%02d_READ_ISSUING {8} " [expr {$i+1}]]
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append cmd [format "CONFIG.M%02d_A00_ADDR_WIDTH {18} " [expr {$i+1}]]
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append cmd [format "CONFIG.M%02d_A00_BASE_ADDR {0x0000000000%02x0000} " [expr {0x10 + $i*4}]]
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}
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}
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append cmd "] \[get_ips shell_xbar]"
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eval $cmd
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#
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# Stripe
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#
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create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_stripe_b
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set_property -dict [list CONFIG.TDATA_NUM_BYTES {0} CONFIG.TUSER_WIDTH {2}] [get_ips axis_data_fifo_stripe_b]
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create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_stripe_r
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set_property -dict [list CONFIG.TDATA_NUM_BYTES {64} CONFIG.TUSER_WIDTH {2} CONFIG.HAS_TLAST {1}] [get_ips axis_data_fifo_stripe_r]
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#
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# Debug
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#
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create_ip -name debug_bridge -vendor xilinx.com -library ip -version 3.0 -module_name debug_bridge_dynamic
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set cmd "set_property -dict \[list CONFIG.C_NUM_BS_MASTER {$cfg(n_reg)} CONFIG.C_DESIGN_TYPE {1}] \[get_ips debug_bridge_dynamic]"
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eval $cmd
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# if {$cfg(en_pr) eq 1} {
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# create_ip -name debug_bridge -vendor xilinx.com -library ip -version 3.0 -module_name debug_bridge_dynamic
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# set cmd "set_property -dict \[list CONFIG.C_NUM_BS_MASTER {$cfg(n_reg)} CONFIG.C_DESIGN_TYPE {1}] \[get_ips debug_bridge_dynamic]"
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# eval $cmd
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# } else {
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# create_ip -name debug_bridge -vendor xilinx.com -library ip -version 3.0 -module_name debug_bridge_dynamic
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# set_property -dict [list CONFIG.C_DEBUG_MODE {1} CONFIG.C_NUM_BS_MASTER {0} CONFIG.C_DESIGN_TYPE {1}] [get_ips debug_bridge_dynamic]
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# }
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create_ip -name vio -vendor xilinx.com -library ip -version 3.0 -module_name vio_shell_xstats
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set_property -dict [list CONFIG.C_PROBE_IN5_WIDTH {32} CONFIG.C_PROBE_IN4_WIDTH {32} CONFIG.C_PROBE_IN3_WIDTH {32} CONFIG.C_PROBE_IN2_WIDTH {32} CONFIG.C_PROBE_IN1_WIDTH {32} CONFIG.C_PROBE_IN0_WIDTH {32} CONFIG.C_NUM_PROBE_OUT {0} CONFIG.C_NUM_PROBE_IN {6}] [get_ips vio_shell_xstats]
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create_ip -name vio -vendor xilinx.com -library ip -version 3.0 -module_name vio_shell_decoupling
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set cmd "set_property -dict \[list CONFIG.C_PROBE_IN0_WIDTH {$cfg(n_reg)} CONFIG.C_PROBE_OUT0_WIDTH {1} CONFIG.C_PROBE_OUT1_WIDTH {$cfg(n_reg)} CONFIG.C_NUM_PROBE_OUT {2} CONFIG.C_NUM_PROBE_IN {1}] \[get_ips vio_shell_decoupling]"
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eval $cmd
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# Control xbars
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for {set i 0} {$i < $cfg(n_reg)} {incr i} {
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set cmd "create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module_name dyn_crossbar_$i"
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eval $cmd
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set offs [expr {0x10 + $i * 4}]
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set cmd [format "set_property -dict \[list \
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CONFIG.NUM_MI {4} CONFIG.ADDR_WIDTH {64} CONFIG.PROTOCOL {AXI4LITE} CONFIG.DATA_WIDTH {64} CONFIG.CONNECTIVITY_MODE {SASD} CONFIG.R_REGISTER {1} \
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CONFIG.S00_WRITE_ACCEPTANCE {1} CONFIG.S01_WRITE_ACCEPTANCE {1} CONFIG.S02_WRITE_ACCEPTANCE {1} CONFIG.S03_WRITE_ACCEPTANCE {1} CONFIG.S04_WRITE_ACCEPTANCE {1} CONFIG.S05_WRITE_ACCEPTANCE {1} CONFIG.S06_WRITE_ACCEPTANCE {1} CONFIG.S07_WRITE_ACCEPTANCE {1} CONFIG.S08_WRITE_ACCEPTANCE {1} CONFIG.S09_WRITE_ACCEPTANCE {1} CONFIG.S10_WRITE_ACCEPTANCE {1} CONFIG.S11_WRITE_ACCEPTANCE {1} CONFIG.S12_WRITE_ACCEPTANCE {1} CONFIG.S13_WRITE_ACCEPTANCE {1} CONFIG.S14_WRITE_ACCEPTANCE {1} CONFIG.S15_WRITE_ACCEPTANCE {1} \
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CONFIG.S00_READ_ACCEPTANCE {1} CONFIG.S01_READ_ACCEPTANCE {1} CONFIG.S02_READ_ACCEPTANCE {1} CONFIG.S03_READ_ACCEPTANCE {1} CONFIG.S04_READ_ACCEPTANCE {1} CONFIG.S05_READ_ACCEPTANCE {1} CONFIG.S06_READ_ACCEPTANCE {1} CONFIG.S07_READ_ACCEPTANCE {1} CONFIG.S08_READ_ACCEPTANCE {1} CONFIG.S09_READ_ACCEPTANCE {1} CONFIG.S10_READ_ACCEPTANCE {1} CONFIG.S11_READ_ACCEPTANCE {1} CONFIG.S12_READ_ACCEPTANCE {1} CONFIG.S13_READ_ACCEPTANCE {1} CONFIG.S14_READ_ACCEPTANCE {1} CONFIG.S15_READ_ACCEPTANCE {1} \
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CONFIG.M00_WRITE_ISSUING {1} CONFIG.M01_WRITE_ISSUING {1} CONFIG.M02_WRITE_ISSUING {1} CONFIG.M03_WRITE_ISSUING {1} CONFIG.M04_WRITE_ISSUING {1} CONFIG.M05_WRITE_ISSUING {1} CONFIG.M06_WRITE_ISSUING {1} CONFIG.M07_WRITE_ISSUING {1} CONFIG.M08_WRITE_ISSUING {1} CONFIG.M09_WRITE_ISSUING {1} CONFIG.M10_WRITE_ISSUING {1} CONFIG.M11_WRITE_ISSUING {1} CONFIG.M12_WRITE_ISSUING {1} CONFIG.M13_WRITE_ISSUING {1} CONFIG.M14_WRITE_ISSUING {1} CONFIG.M15_WRITE_ISSUING {1} \
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CONFIG.M00_READ_ISSUING {1} CONFIG.M01_READ_ISSUING {1} CONFIG.M02_READ_ISSUING {1} CONFIG.M03_READ_ISSUING {1} CONFIG.M04_READ_ISSUING {1} CONFIG.M05_READ_ISSUING {1} CONFIG.M06_READ_ISSUING {1} CONFIG.M07_READ_ISSUING {1} CONFIG.M08_READ_ISSUING {1} CONFIG.M09_READ_ISSUING {1} CONFIG.M10_READ_ISSUING {1} CONFIG.M11_READ_ISSUING {1} CONFIG.M12_READ_ISSUING {1} CONFIG.M13_READ_ISSUING {1} CONFIG.M14_READ_ISSUING {1} CONFIG.M15_READ_ISSUING {1} \
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CONFIG.S00_SINGLE_THREAD {1} CONFIG.M00_A00_BASE_ADDR {0x0000000000%02x0000} CONFIG.M01_A00_BASE_ADDR {0x0000000000%02x0000} CONFIG.M02_A00_BASE_ADDR {0x0000000000%02x0000} CONFIG.M03_A00_BASE_ADDR {0x0000000000%02x0000} CONFIG.M00_A00_ADDR_WIDTH {16} CONFIG.M01_A00_ADDR_WIDTH {16} CONFIG.M02_A00_ADDR_WIDTH {16} CONFIG.M03_A00_ADDR_WIDTH {16} \
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] \[get_ips dyn_crossbar_$i]" $offs [expr {$offs + 1}] [expr {$offs + 2}] [expr {$offs + 3}] ]
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eval $cmd
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}
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# TLB
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create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_128_tlb
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set_property -dict [list CONFIG.TDATA_NUM_BYTES {16} CONFIG.FIFO_DEPTH {64} CONFIG.HAS_TLAST {1} ] [get_ips axis_data_fifo_128_tlb]
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create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_cch_req_128
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set_property -dict [list CONFIG.TDATA_NUM_BYTES {16} CONFIG.FIFO_DEPTH {256} ] [get_ips axis_data_fifo_cch_req_128]
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create_ip -name axis_interconnect -vendor xilinx.com -library ip -version 1.1 -module_name axis_interconnect_tlb
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set_property -dict [list CONFIG.C_NUM_SI_SLOTS {2} CONFIG.SWITCH_TDATA_NUM_BYTES {16} CONFIG.HAS_TSTRB {false} CONFIG.HAS_TKEEP {false} CONFIG.HAS_TLAST {true} CONFIG.HAS_TID {false} CONFIG.HAS_TDEST {false} CONFIG.SWITCH_PACKET_MODE {false} CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {1} CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} CONFIG.M00_AXIS_TDATA_NUM_BYTES {16} CONFIG.S00_AXIS_TDATA_NUM_BYTES {16} CONFIG.S01_AXIS_TDATA_NUM_BYTES {16} CONFIG.M00_S01_CONNECTIVITY {true}] [get_ips axis_interconnect_tlb]
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# Bypass ic
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create_ip -name axis_interconnect -vendor xilinx.com -library ip -version 1.1 -module_name axis_interconnect_cnfg_req_arbiter
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set_property -dict [list CONFIG.C_NUM_SI_SLOTS {2} CONFIG.SWITCH_TDATA_NUM_BYTES {12} CONFIG.HAS_TSTRB {false} CONFIG.HAS_TKEEP {false} CONFIG.HAS_TLAST {false} CONFIG.HAS_TID {false} CONFIG.HAS_TDEST {false} CONFIG.C_M00_AXIS_REG_CONFIG {1} CONFIG.SWITCH_PACKET_MODE {false} CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {1} CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} CONFIG.M00_AXIS_TDATA_NUM_BYTES {12} CONFIG.S00_AXIS_TDATA_NUM_BYTES {12} CONFIG.S01_AXIS_TDATA_NUM_BYTES {12} CONFIG.M00_S01_CONNECTIVITY {true}] [get_ips axis_interconnect_cnfg_req_arbiter]
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# Converters
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create_ip -name axis_dwidth_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_dwidth_converter_tlb
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set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {64} CONFIG.M_TDATA_NUM_BYTES {16} CONFIG.HAS_TLAST {1} CONFIG.HAS_TKEEP {1} ] [get_ips axis_dwidth_converter_tlb]
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update_compile_order -fileset sources_1
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