99 lines
4.2 KiB
Tcl
99 lines
4.2 KiB
Tcl
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########################################################################################################
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# USER LAYER
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########################################################################################################
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puts "[color $clr_flow "** Creating user projects ..."]"
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puts "[color $clr_flow "**"]"
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for {set i 0} {$i < $cfg(n_config)} {incr i} {
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for {set j 0} {$j < $cfg(n_reg)} {incr j} {
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set proj_dir "$build_dir/$project\_config_$i/user\_c$i\_$j"
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########################################################################################################
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# Project
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########################################################################################################
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create_project $project $proj_dir -part $part -force
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set proj [current_project]
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set_property IP_REPO_PATHS $lib_dir [current_fileset]
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update_ip_catalog
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file mkdir "$dcp_dir/config_$i"
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file mkdir "$rprt_dir/config_$i"
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file mkdir "$log_dir/config_$i"
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########################################################################################################
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# Set project properties
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########################################################################################################
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#set_property "board_part" $board_part $proj
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set_property "default_lib" "xil_defaultlib" $proj
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set_property "ip_cache_permissions" "read write" $proj
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set_property "ip_output_repo" "$proj_dir/$project.cache/ip" $proj
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set_property "sim.ip.auto_export_scripts" "1" $proj
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set_property "target_language" "Verilog" $proj
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set_property "simulator_language" "Mixed" $proj
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set_property "xpm_libraries" "XPM_CDC XPM_MEMORY" $proj
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########################################################################################################
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# Create and add source files
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########################################################################################################
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file mkdir "$proj_dir/hdl"
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file mkdir "$proj_dir/hdl/ext"
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file mkdir "$proj_dir/hdl/wrappers"
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file mkdir "$proj_dir/xdc"
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# Call write HDL scripts
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proc call_write_hdl {r_path op c_cnfg c_reg} {
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set output [exec /usr/bin/python3 "$r_path/write_hdl.py" $op $c_cnfg $c_reg]
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puts $output
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}
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call_write_hdl $build_dir 2 $i $j
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# Add source files
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add_files "$hw_dir/hdl/shell/user_lback.svh"
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add_files "$hw_dir/hdl/pkg"
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add_files "$hw_dir/hdl/user"
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add_files "$hw_dir/hdl/common"
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add_files "$proj_dir/hdl"
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add_files "$proj_dir/hdl/wrappers"
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# Top level
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set_property "top" design_user_wrapper_$j [current_fileset]
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# Constraints
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add_files -norecurse -fileset [get_filesets constrs_1] "$proj_dir/xdc"
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set_property used_in_implementation false [get_files -of_objects [get_filesets constrs_1]]
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#set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-mode out_of_context} -objects [get_runs synth_1]
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# Create a project-local constraint file to take debugging constraints that we
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# don't want to propagate to the repository.
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file mkdir "$proj_dir/$project.srcs/constrs_1"
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close [ open "$proj_dir/$project.srcs/constrs_1/local.xdc" w ]
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set_property target_constrs_file "$proj_dir/$project.srcs/constrs_1/local.xdc" [current_fileset -constrset]
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# User infrastructure
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source "$scripts_dir/ip_inst/user_infrastructure.tcl" -notrace
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source "$scripts_dir/ip_inst/common_infrastructure.tcl" -notrace
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# Close
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close_project
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# User
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puts "[color $clr_flow "** vFPGA_C$i\_$j project created"]"
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puts "[color $clr_flow "**"]"
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}
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}
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########################################################################################################
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# PACKAGE IP
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########################################################################################################
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if {$cfg(load_apps) eq 1} {
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source "$build_dir/package.tcl"
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}
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puts "[color $clr_flow "** User projects created"]"
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puts "[color $clr_flow "**"]"
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