112 lines
4.2 KiB
Tcl
112 lines
4.2 KiB
Tcl
########################################################################################################
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# Project
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########################################################################################################
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puts "[color $clr_flow "** Creating static project ..."]"
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puts "[color $clr_flow "**"]"
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set proj_dir "$build_dir/$project\_static"
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# Check iprepo
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if { [file isdirectory $iprepo_dir] } {
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set lib_dir "$iprepo_dir"
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} else {
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puts "iprepo directory could not be found."
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#exit 1
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}
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# Create project
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create_project $project $proj_dir -part $part -force
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set proj [current_project]
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set_property IP_REPO_PATHS $lib_dir [current_fileset]
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update_ip_catalog
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set_msg_config -id {Vivado 12-2924} -suppress
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set_msg_config -id {IP_Flow 19-4832} -suppress
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file mkdir "$dcp_dir/static"
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file mkdir "$rprt_dir/static"
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file mkdir "$log_dir/static"
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########################################################################################################
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# Set project properties
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########################################################################################################
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#set_property "board_part" $board_part $proj
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set_property "default_lib" "xil_defaultlib" $proj
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set_property "ip_cache_permissions" "read write" $proj
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set_property "ip_output_repo" "$proj_dir/$project.cache/ip" $proj
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set_property "sim.ip.auto_export_scripts" "1" $proj
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set_property "target_language" "Verilog" $proj
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set_property "simulator_language" "Mixed" $proj
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set_property "xpm_libraries" "XPM_CDC XPM_MEMORY" $proj
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########################################################################################################
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# Create and add source files
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########################################################################################################
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file mkdir "$proj_dir/hdl/static"
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# Call write HDL scripts
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proc call_write_hdl {r_path op c_cnfg c_reg} {
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set output [exec /usr/bin/python3 "$r_path/write_hdl.py" $op $c_cnfg $c_cnfg]
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puts $output
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}
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call_write_hdl $build_dir 0 0 0
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# Add source files
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add_files "$hw_dir/hdl/pkg"
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add_files "$hw_dir/hdl/static"
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add_files "$proj_dir/hdl/static"
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if {$cfg(fdev) eq "enzian"} {
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add_files "$hw_dir/hdl/eci"
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add_files "$hw_dir/enzian_eci_transport/hdl"
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add_files "$hw_dir/enzian_eci_toolkit/hdl"
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}
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# Top level
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set_property "top" "cyt_top" [current_fileset]
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# Constraints
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add_files -norecurse -fileset [get_filesets constrs_1] "$hw_dir/constraints/$cfg(fdev)/static/synth"
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set_property used_in_implementation false [get_files -of_objects [get_filesets constrs_1]]
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# Create a project-local constraint file to take debugging constraints that we
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# don't want to propagate to the repository.
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file mkdir "$proj_dir/$project.srcs/constrs_1"
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close [ open "$proj_dir/$project.srcs/constrs_1/local.xdc" w ]
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set_property target_constrs_file "$proj_dir/$project.srcs/constrs_1/local.xdc" [current_fileset -constrset]
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########################################################################################################
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# STATIC INFRASTRUCTURE
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########################################################################################################
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if {$cfg(fdev) eq "enzian"} {
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source "$scripts_dir/ip_inst/eci_infrastructure.tcl" -notrace
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} else {
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source "$scripts_dir/ip_inst/pci_infrastructure.tcl" -notrace
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}
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########################################################################################################
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# STATIC BLOCK DESIGN
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########################################################################################################
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if {$cfg(fdev) eq "enzian"} {
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source "$scripts_dir/bd/cr_eci.tcl" -notrace
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cr_bd_design_static ""
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set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_static.bd ]
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} else {
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source "$scripts_dir/bd/cr_pci.tcl" -notrace
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cr_bd_design_static ""
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set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_static.bd ]
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}
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########################################################################################################
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# STATIC PROJECT CREATED
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########################################################################################################
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close_project
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puts "[color $clr_flow "** Static project created"]"
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puts "[color $clr_flow "**"]"
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