140 lines
5.1 KiB
Tcl
140 lines
5.1 KiB
Tcl
if {[catch {
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########################################################################################################
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source "${CMAKE_BINARY_DIR}/base.tcl"
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########################################################################################################
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# Project
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########################################################################################################
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file mkdir "$build_dir/sim"
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set sim_dir "$build_dir/sim"
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puts $sim_dir
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set proj_dir "$build_dir/$project\_shell"
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# Create project
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create_project $project $sim_dir -part $part -force
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set proj [current_project]
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puts "**** Sim created"
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puts "****"
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########################################################################################################
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# Set project properties
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########################################################################################################
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#set_property "board_part" $board_part $proj
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set_property "default_lib" "xil_defaultlib" $proj
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set_property "ip_cache_permissions" "read write" $proj
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set_property "ip_output_repo" "$sim_dir/$project.cache/ip" $proj
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set_property "sim.ip.auto_export_scripts" "1" $proj
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set_property "target_language" "Verilog" $proj
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set_property "simulator_language" "Mixed" $proj
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set_property "xpm_libraries" "XPM_CDC XPM_MEMORY" $proj
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if {$cfg(en_pr) eq 1} {
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set_property "pr_flow" "1" $proj
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}
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puts "**** Sim properties set"
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puts "****"
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########################################################################################################
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# Create and add source files
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########################################################################################################
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# Create 'sources_1' fileset (if not found)
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if {[string equal [get_filesets -quiet sources_1] ""]} {
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create_fileset -srcset sources_1
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}
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# Copy base
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file mkdir "$sim_dir/hdl"
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exec cp "$hw_dir/sim/tb_templates/tb_user.sv" "$sim_dir/hdl"
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exec cp "$hw_dir/sim/tb_templates/tb_design_user_logic.sv" "$sim_dir/hdl"
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exec cp "$hw_dir/sim/tb_templates/c_gen.svh" "$sim_dir/hdl"
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exec cp "$hw_dir/sim/tb_templates/c_scb.svh" "$sim_dir/hdl"
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exec cp "$hw_dir/sim/tb_templates/c_struct.sv" "$sim_dir/hdl"
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# Call write HDL scripts
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unset ::env(PYTHONPATH)
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unset ::env(PYTHONHOME)
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proc call_write_hdl {r_path op c_cnfg c_reg} {
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set output [exec /usr/bin/python3 "$r_path/write_hdl.py" $op $c_cnfg $c_cnfg]
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puts $output
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}
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call_write_hdl "$build_dir" 3 0 0
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# Set 'sources_1' fileset object
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set obj [get_filesets sources_1]
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set files [list \
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[file normalize "$sim_dir/hdl/lynx_pkg.sv"] \
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[file normalize "$sim_dir/hdl/tb_user.sv"] \
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[file normalize "$sim_dir/hdl/tb_design_user_logic.sv"] \
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[file normalize "$sim_dir/hdl/c_gen.svh"] \
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[file normalize "$sim_dir/hdl/c_scb.svh"] \
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[file normalize "$sim_dir/hdl/c_struct.sv"] \
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[file normalize "$hw_dir/sim/tb_env/c_trs.svh"] \
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[file normalize "$hw_dir/sim/tb_env/c_axil.svh"] \
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[file normalize "$hw_dir/sim/tb_env/c_axi.svh"] \
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[file normalize "$hw_dir/sim/tb_env/c_meta.svh"] \
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[file normalize "$hw_dir/sim/tb_env/c_drv.svh"] \
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[file normalize "$hw_dir/sim/tb_env/c_mon.svh"] \
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[file normalize "$hw_dir/sim/tb_env/c_env.svh"] \
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[file normalize "$hw_dir/hdl/pkg/axi_intf.sv"] \
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[file normalize "$hw_dir/hdl/pkg/lynx_intf.sv"] \
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[file normalize "$hw_dir/hdl/pkg/axi_macros.svh"] \
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[file normalize "$hw_dir/hdl/pkg/lynx_macros.svh"] \
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[file normalize "$hw_dir/hdl/common/queues/fifo.sv"] \
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[file normalize "$hw_dir/hdl/common/queues/queue_stream.sv"] \
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[file normalize "$hw_dir/hdl/common/queues/queue_meta.sv"] \
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[file normalize "$hw_dir/hdl/common/queues/queue.sv"] \
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[file normalize "$hw_dir/hdl/common/ram/tdp_ram_c.sv"] \
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[file normalize "$hw_dir/hdl/common/ram/tdp_ram_nc.sv"] \
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[file normalize "$hw_dir/hdl/common/regs/axisr_reg_rtl.sv"] \
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[file normalize "$hw_dir/hdl/common/regs/axil_reg_rtl.sv"] \
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[file normalize "$hw_dir/hdl/common/regs/axil_reg_rd.v"] \
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[file normalize "$hw_dir/hdl/common/regs/axil_reg_wr.v"] \
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[file normalize "$hw_dir/hdl/common/regs/meta_reg_rtl.sv"] \
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]
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add_files -norecurse -fileset $obj $files
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set_property top tb_user [current_fileset]
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set_property top tb_user [get_filesets sim_1]
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set_property top_lib xil_defaultlib [get_filesets sim_1]
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puts "**** Sim sources set"
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puts "****"
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########################################################################################################
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# Simulation
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########################################################################################################
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# puts "**** Launching sim ..."
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# puts "****"
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#
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# launch_simulation
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#
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# puts "**** Simulation completed"
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# puts "****"
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########################################################################################################
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# CUSTOM SCRIPTS
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########################################################################################################
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if {$cfg(sim_path) != "0"} {
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source "${SIM_SCR_PATH}" -notrace
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puts "**** Custom sim script"
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puts "****"
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}
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########################################################################################################
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} errorstring]} {
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puts "**** CERR: $errorstring"
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puts "****"
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exit 1
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}
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exit 0
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