372 lines
9.8 KiB
Systemverilog
372 lines
9.8 KiB
Systemverilog
import lynxTypes::*;
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/**
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* PT Config Slave
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*/
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module send_recv_slave (
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input logic aclk,
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input logic aresetn,
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AXI4L.s axi_ctrl,
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output logic ap_start,
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input logic ap_done,
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output logic [31:0] useConn,
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output logic [31:0] useIpAddr,
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output logic [31:0] pkgWordCount,
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output logic [31:0] basePort,
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output logic [31:0] baseIpAddress,
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output logic [31:0] transferSize,
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output logic [31:0] isServer,
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output logic [31:0] timeInSeconds,
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output logic [63:0] timeInCycles,
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input logic [63:0] execution_cycles,
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input logic [63:0] consumed_bytes,
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input logic [63:0] produced_bytes,
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input logic [63:0] openCon_cycles
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);
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// `define DEBUG_CNFG_SLAVE
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// -- Decl ----------------------------------------------------------
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// ------------------------------------------------------------------
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// Constants
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localparam integer N_REGS = 15;
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localparam integer ADDR_LSB = $clog2(AXIL_DATA_BITS/8);
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localparam integer ADDR_MSB = $clog2(N_REGS);
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localparam integer AXIL_ADDR_BITS = ADDR_LSB + ADDR_MSB;
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// Internal registers
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logic [AXIL_ADDR_BITS-1:0] axi_awaddr;
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logic axi_awready;
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logic [AXIL_ADDR_BITS-1:0] axi_araddr;
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logic axi_arready;
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logic [1:0] axi_bresp;
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logic axi_bvalid;
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logic axi_wready;
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logic [AXIL_DATA_BITS-1:0] axi_rdata;
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logic [1:0] axi_rresp;
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logic axi_rvalid;
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// Registers
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logic [N_REGS-1:0][AXIL_DATA_BITS-1:0] slv_reg;
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logic slv_reg_rden;
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logic slv_reg_wren;
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logic aw_en;
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// -- Def -----------------------------------------------------------
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// ------------------------------------------------------------------
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/* -- Register map -----------------------------------------------------------------------
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/ 0 (WO) : Control
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/ 1 (RO) : Status
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/ 2 (RW) : useConn
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/ 3 (RW) : useIpAddr
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/ 4 (RW) : pkgWordCount
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/ 5 (RW) : basePort
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/ 6 (RW) : baseIpAddr
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/ 7 (RW) : transferSize
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/ 8 (RW) : isServer
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/ 9 (RW) : timeInSeconds
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/ 10 (RW) : timeInCycles
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/ 11 (R) : execution_cycles
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/ 12 (R) : consumed_bytes
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/ 13 (R) : produced_bytes
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/ 14 (R) : openCon_cycles
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*/
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// Write process
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assign slv_reg_wren = axi_wready && axi_ctrl.wvalid && axi_awready && axi_ctrl.awvalid;
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always_ff @(posedge aclk) begin
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if ( aresetn == 1'b0 ) begin
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slv_reg <= 0;
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end
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else begin
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slv_reg[0][0] <= 0;
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if(slv_reg_wren) begin
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case (axi_awaddr[ADDR_LSB+:ADDR_MSB])
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4'h0: // Control
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for (int i = 0; i < 1; i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[0][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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end
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end
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4'h2: // useConn
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for (int i = 0; i < AXIL_DATA_BITS/8; i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[2][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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end
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end
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4'h3: // useIpAddr
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for (int i = 0; i < AXIL_DATA_BITS/8; i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[3][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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end
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end
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4'h4: // pkgWordCount
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for (int i = 0; i < AXIL_DATA_BITS/8; i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[4][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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end
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end
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4'h5: // basePort
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for (int i = 0; i < AXIL_DATA_BITS/8; i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[5][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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end
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end
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4'h6: // baseIpAddr
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for (int i = 0; i < AXIL_DATA_BITS/8; i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[6][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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end
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end
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4'h7: // transferSize
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for (int i = 0; i < AXIL_DATA_BITS/8; i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[7][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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end
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end
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4'h8: // isServer
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for (int i = 0; i < AXIL_DATA_BITS/8; i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[8][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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end
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end
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4'h9: // timeInSeconds
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for (int i = 0; i < AXIL_DATA_BITS/8; i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[9][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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end
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end
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4'ha: // timeInCycles
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for (int i = 0; i < AXIL_DATA_BITS/8; i++) begin
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if(axi_ctrl.wstrb[i]) begin
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slv_reg[10][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8];
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end
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end
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default : ;
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endcase
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end
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end
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end
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// Output
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always_comb begin
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ap_start = slv_reg[0][0];
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useConn = slv_reg[2];
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useIpAddr = slv_reg[3];
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pkgWordCount = slv_reg[4];
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basePort = slv_reg[5];
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baseIpAddress = slv_reg[6];
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transferSize = slv_reg[7];
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isServer = slv_reg[8];
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timeInSeconds = slv_reg[9];
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timeInCycles = slv_reg[10];
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end
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// Read process
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assign slv_reg_rden = axi_arready & axi_ctrl.arvalid & ~axi_rvalid;
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always_ff @(posedge aclk) begin
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if( aresetn == 1'b0 ) begin
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axi_rdata <= 0;
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end
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else begin
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if(slv_reg_rden) begin
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axi_rdata <= 0;
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case (axi_araddr[ADDR_LSB+:ADDR_MSB])
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4'h1: // Status
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axi_rdata[0] <= ap_done;
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4'h2: // useConn
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axi_rdata <= slv_reg[2];
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4'h3: // useIpAddr
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axi_rdata <= slv_reg[3];
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4'h4: // pkgWordCount
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axi_rdata <= slv_reg[4];
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4'h5: // basePort
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axi_rdata <= slv_reg[5];
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4'h6: // baseIpAddr
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axi_rdata <= slv_reg[6];
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4'h7: // transferSize
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axi_rdata <= slv_reg[7];
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4'h8: // isServer
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axi_rdata <= slv_reg[8];
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4'h9: // timeInSeconds
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axi_rdata <= slv_reg[9];
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4'ha: // timeInCycles
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axi_rdata <= slv_reg[10];
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4'hb: //execution_cycles
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axi_rdata <= execution_cycles;
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4'hc: //consumed_bytes
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axi_rdata <= consumed_bytes;
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4'hd: //produced_bytes
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axi_rdata <= produced_bytes;
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4'he: //openCon_cycles
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axi_rdata <= openCon_cycles;
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default: ;
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endcase
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end
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end
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end
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//`define DEBUG_CNFG_SLAVE
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`ifdef DEBUG_CNFG_SLAVE
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ila_slave ila_slave
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(
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.clk(aclk),
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.probe0(slv_reg_rden),
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.probe1(slv_reg_wren),
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.probe2(axi_ctrl.arvalid),
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.probe3(axi_ctrl.arready),
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.probe4(axi_ctrl.araddr), // 64
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.probe5(axi_ctrl.awvalid),
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.probe6(axi_ctrl.awready),
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.probe7(axi_ctrl.awaddr), // 64
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.probe8(axi_ctrl.rvalid),
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.probe9(axi_ctrl.rready),
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.probe10(axi_ctrl.rdata), // 64
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.probe11(axi_ctrl.wvalid),
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.probe12(axi_ctrl.wready),
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.probe13(axi_ctrl.wdata), // 64
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.probe14(axi_ctrl.wstrb), // 8
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.probe15(axi_ctrl.bvalid),
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.probe16(axi_ctrl.bready)
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);
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`endif
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// --------------------------------------------------------------------------------------
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// AXI CTRL
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// --------------------------------------------------------------------------------------
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// Don't edit
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// I/O
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assign axi_ctrl.awready = axi_awready;
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assign axi_ctrl.arready = axi_arready;
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assign axi_ctrl.bresp = axi_bresp;
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assign axi_ctrl.bvalid = axi_bvalid;
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assign axi_ctrl.wready = axi_wready;
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assign axi_ctrl.rdata = axi_rdata;
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assign axi_ctrl.rresp = axi_rresp;
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assign axi_ctrl.rvalid = axi_rvalid;
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// awready and awaddr
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always_ff @(posedge aclk) begin
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if ( aresetn == 1'b0 )
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begin
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axi_awready <= 1'b0;
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axi_awaddr <= 0;
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aw_en <= 1'b1;
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end
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else
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begin
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if (~axi_awready && axi_ctrl.awvalid && axi_ctrl.wvalid && aw_en)
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begin
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axi_awready <= 1'b1;
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aw_en <= 1'b0;
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axi_awaddr <= axi_ctrl.awaddr;
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end
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else if (axi_ctrl.bready && axi_bvalid)
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begin
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aw_en <= 1'b1;
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axi_awready <= 1'b0;
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end
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else
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begin
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axi_awready <= 1'b0;
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end
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end
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end
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// arready and araddr
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always_ff @(posedge aclk) begin
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if ( aresetn == 1'b0 )
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begin
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axi_arready <= 1'b0;
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axi_araddr <= 0;
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end
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else
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begin
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if (~axi_arready && axi_ctrl.arvalid)
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begin
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axi_arready <= 1'b1;
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axi_araddr <= axi_ctrl.araddr;
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end
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else
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begin
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axi_arready <= 1'b0;
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end
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end
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end
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// bvalid and bresp
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always_ff @(posedge aclk) begin
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if ( aresetn == 1'b0 )
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begin
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axi_bvalid <= 0;
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axi_bresp <= 2'b0;
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end
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else
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begin
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if (axi_awready && axi_ctrl.awvalid && ~axi_bvalid && axi_wready && axi_ctrl.wvalid)
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begin
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axi_bvalid <= 1'b1;
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axi_bresp <= 2'b0;
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end
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else
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begin
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if (axi_ctrl.bready && axi_bvalid)
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begin
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axi_bvalid <= 1'b0;
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end
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end
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end
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end
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// wready
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always_ff @(posedge aclk) begin
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if ( aresetn == 1'b0 )
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begin
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axi_wready <= 1'b0;
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end
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else
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begin
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if (~axi_wready && axi_ctrl.wvalid && axi_ctrl.awvalid && aw_en )
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begin
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axi_wready <= 1'b1;
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end
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else
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begin
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axi_wready <= 1'b0;
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end
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end
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end
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// rvalid and rresp (1Del?)
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always_ff @(posedge aclk) begin
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if ( aresetn == 1'b0 )
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begin
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axi_rvalid <= 0;
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axi_rresp <= 0;
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end
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else
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begin
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if (axi_arready && axi_ctrl.arvalid && ~axi_rvalid)
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begin
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axi_rvalid <= 1'b1;
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axi_rresp <= 2'b0;
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end
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else if (axi_rvalid && axi_ctrl.rready)
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begin
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axi_rvalid <= 1'b0;
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end
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end
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end
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endmodule // cnfg_slave
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