35 lines
955 B
Tcl
35 lines
955 B
Tcl
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open_project ${PROJECT_NAME}_prj
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open_solution "solution1"
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set_part ${FPGA_PART}
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create_clock -period ${CLOCK_PERIOD} -name default
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set_top ${PROJECT_NAME}
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add_files ${CMAKE_CURRENT_SOURCE_DIR}/send_recv.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}"
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add_files -tb ${CMAKE_CURRENT_SOURCE_DIR}/test_send_recv.cpp
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#Check which command
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set command [lindex $argv 2]
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if {$command == "synthesis"} {
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csynth_design
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} elseif {$command == "csim"} {
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csim_design
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} elseif {$command == "ip"} {
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export_design -format ip_catalog -ipname "send_recv" -display_name "send_recv" -vendor "ethz.systems.fpga" -version "1.0"
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} elseif {$command == "services"} {
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file mkdir ${IPREPO_DIR}
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file delete -force ${IPREPO_DIR}/${PROJECT_NAME}
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file copy -force ${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}_prj/solution1/impl/ip ${IPREPO_DIR}/${PROJECT_NAME}/
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} else {
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puts "No valid command specified. Use vitis_hls -f make.tcl <synthesis|csim|ip> ."
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}
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exit
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