65 lines
1.7 KiB
Systemverilog
65 lines
1.7 KiB
Systemverilog
/**
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* VFPGA TOP
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*
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* Tie up all signals to the user kernels
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* Still to this day, interfaces are not supported by Vivado packager ...
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* This means verilog style port connections are needed.
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*
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*/
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always_comb begin
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// Write ops
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sq_wr.valid = rq_wr.valid;
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rq_wr.ready = sq_wr.ready;
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sq_wr.data = rq_wr.data;
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// OW
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sq_wr.data.strm = STRM_HOST;
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sq_wr.data.dest = is_opcode_rd_resp(rq_wr.data.opcode) ? 0 : 1;
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// Read ops
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sq_rd.valid = rq_rd.valid;
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rq_rd.ready = sq_rd.ready;
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sq_rd.data = rq_rd.data;
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// OW
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sq_rd.data.strm = STRM_HOST;
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sq_rd.data.dest = 1;
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end
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`AXISR_ASSIGN(axis_host_recv[0], axis_rreq_send[0])
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`AXISR_ASSIGN(axis_rreq_recv[0], axis_host_send[0])
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`AXISR_ASSIGN(axis_host_recv[1], axis_rrsp_send[0])
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`AXISR_ASSIGN(axis_rrsp_recv[0], axis_host_send[1])
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ila_0 inst_ila (
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.clk(aclk),
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.probe0(axis_host_recv[0].tvalid),
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.probe1(axis_host_recv[0].tready),
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.probe2(axis_host_recv[0].tlast),
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.probe3(axis_host_recv[1].tvalid),
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.probe4(axis_host_recv[1].tready),
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.probe5(axis_host_recv[1].tlast),
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.probe6(axis_host_send[0].tvalid),
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.probe7(axis_host_send[0].tready),
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.probe8(axis_host_send[0].tlast),
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.probe9(axis_host_send[1].tvalid),
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.probe10(axis_host_send[1].tready),
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.probe11(axis_host_send[1].tlast),
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.probe12(sq_wr.valid),
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.probe13(sq_wr.ready),
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.probe14(sq_wr.data), // 128
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.probe15(sq_rd.valid),
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.probe16(sq_rd.ready),
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.probe17(sq_rd.data), // 128
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.probe18(cq_rd.valid),
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.probe19(cq_wr.valid)
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);
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// Tie-off unused
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always_comb axi_ctrl.tie_off_s();
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always_comb notify.tie_off_m();
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always_comb cq_rd.tie_off_s();
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always_comb cq_wr.tie_off_s(); |