51 lines
1013 B
Systemverilog
51 lines
1013 B
Systemverilog
/**
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* VFPGA TOP
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*
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* Tie up all signals to the user kernels
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* Still to this day, interfaces are not supported by Vivado packager ...
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* This means verilog style port connections are needed.
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*
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*/
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// CSR
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logic [PID_BITS-1:0] mux_ctid; // go to card with this ctid
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rdma_base_slv inst_rdma_base_slv (
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.aclk(aclk),
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.aresetn(aresetn),
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.axi_ctrl(axi_ctrl),
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.mux_ctid(mux_ctid)
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);
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mux_host_card_rd_rdma inst_mux_send (
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.aclk(aclk),
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.aresetn(aresetn),
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.mux_ctid(mux_ctid),
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.s_rq(rq_rd),
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.m_sq(sq_rd),
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.s_axis_host(axis_host_recv[0]),
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.s_axis_card(axis_card_recv[0]),
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.m_axis(axis_rdma_send[0])
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);
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mux_host_card_wr_rdma inst_mux_recv (
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.aclk(aclk),
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.aresetn(aresetn),
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.mux_ctid(mux_ctid),
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.s_rq(rq_wr),
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.m_sq(sq_wr),
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.s_axis(axis_rdma_recv[0]),
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.m_axis_host(axis_host_send[0]),
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.m_axis_card(axis_card_send[0])
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);
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// Tie-off unused
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always_comb notify.tie_off_m();
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always_comb cq_rd.tie_off_s();
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always_comb cq_wr.tie_off_s(); |