158 lines
3.2 KiB
Systemverilog
158 lines
3.2 KiB
Systemverilog
/**
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* VFPGA TOP
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*
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* Tie up all signals to the user kernels
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* Still to this day, interfaces are not supported by Vivado packager ...
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* This means verilog style port connections are needed.
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*
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*/
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// Consts
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localparam integer N_AES_PIPELINES = 4;
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localparam integer KEY_ROUNDS = 11;
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// CSR
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logic [PID_BITS-1:0] mux_ctid; // go to card with this ctid
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logic [128*KEY_ROUNDS-1:0] key_dec;
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logic [128*KEY_ROUNDS-1:0] key_enc;
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logic [128-1:0] key_slv;
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logic key_start;
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rdma_aes_slv inst_rdma_aes_slv (
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.aclk(aclk),
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.aresetn(aresetn),
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.axi_ctrl(axi_ctrl),
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.key_out(key_slv),
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.keyStart(key_start),
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.mux_ctid(mux_ctid)
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);
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AXI4SR axis_s0_send ();
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AXI4SR axis_s0_recv ();
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mux_host_card_rd_rdma inst_mux_send (
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.aclk(aclk),
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.aresetn(aresetn),
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.mux_ctid(mux_ctid),
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.s_rq(rq_rd),
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.m_sq(sq_rd),
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.s_axis_host(axis_host_recv[0]),
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.s_axis_card(axis_card_recv[0]),
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.m_axis(axis_s0_send)
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);
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mux_host_card_wr_rdma inst_mux_recv (
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.aclk(aclk),
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.aresetn(aresetn),
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.mux_ctid(mux_ctid),
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.s_rq(rq_wr),
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.m_sq(sq_wr),
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.s_axis(axis_s0_recv),
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.m_axis_host(axis_host_send[0]),
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.m_axis_card(axis_card_send[0])
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);
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//
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// AES encryption and decryption
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//
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// Key decryption
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key_top #(
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.OPERATION(1)
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) inst_key_top_dec (
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.clk(aclk),
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.reset_n(aresetn),
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.stall(1'b0),
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.key_in(key_slv),
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.keyVal_in(keyStart),
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.keyVal_out(),
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.key_out(key_dec)
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);
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// AES pipeline - receive (decrypt)
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aes_top #(
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.NPAR(N_AES_PIPELINES),
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.OPERATION(1), // 0 - enc, 1 - dec
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.MODE(0) // 0 - ECB, 1 - CTR, 2 - CBC
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) inst_aes_top_dec (
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.clk(aclk),
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.reset_n(aresetn),
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.stall(~axis_s0_recv.tready),
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// Key
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.key_in(key_dec),
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//
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.last_in(axis_rdma_recv[0].tlast),
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.last_out(axis_s0_recv.tlast),
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.keep_in(axis_rdma_recv[0].tkeep),
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.keep_out(axis_s0_recv.tkeep),
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// Data
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.dVal_in(axis_rdma_recv[0].tvalid),
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.dVal_out(axis_s0_recv.tvalid),
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.data_in(axis_rdma_recv[0].tdata),
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.data_out(axis_s0_recv.tdata),
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// Counter mode
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.cntr_in(0)
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);
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assign axis_rdma_recv[0].tready = axis_s0_recv.tready;
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assign axis_s0_recv.tid = 0;
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// Key encryption
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key_top #(
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.OPERATION(1)
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) inst_key_top_enc (
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.clk(aclk),
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.reset_n(aresetn),
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.stall(1'b0),
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.key_in(key_slv),
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.keyVal_in(keyStart),
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.keyVal_out(),
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.key_out(key_enc)
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);
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// AES pipeline - send (encrypt)
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aes_top #(
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.NPAR(N_AES_PIPELINES),
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.OPERATION(0), // 0 - enc, 1 - dec
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.MODE(0) // 0 - ECB, 1 - CTR, 2 - CBC
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) inst_aes_top_enc (
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.clk(aclk),
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.reset_n(aresetn),
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.stall(~axis_rdma_send[0].tready),
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// Key
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.key_in(key),
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//
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.last_in(axis_s0_send.tlast),
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.last_out(axis_rdma_send[0].tlast),
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.keep_in(axis_s0_send.tkeep),
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.keep_out(axis_rdma_send[0].tkeep),
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// Data
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.dVal_in(axis_s0_send.tvalid),
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.dVal_out(axis_rdma_send[0].tvalid),
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.data_in(axis_s0_send.tdata),
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.data_out(axis_rdma_send[0].tdata),
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// Counter mode
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.cntr_in(0)
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);
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assign axis_s0_send.tready = axis_rdma_send[0].tready;
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assign axis_rdma_send[0].tid = 0;
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//
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// Tie-off unused
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//
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always_comb notify.tie_off_m();
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always_comb cq_wr.tie_off_s();
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always_comb cq_rd.tie_off_s(); |