54 lines
1.4 KiB
VHDL
54 lines
1.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity shift_rows is
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port(
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data_in : in std_logic_vector(127 downto 0);
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data_out : out std_logic_vector(127 downto 0)
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);
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end entity shift_rows;
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architecture RTL of shift_rows is
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-- Internal signals
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type data_array is array (15 downto 0) of std_logic_vector(7 downto 0);
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signal in_array, out_array : data_array;
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begin
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-- Input generation
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GEN_IN: for i in 15 downto 0 generate
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in_array(15-i) <= data_in(i*8+7 downto i*8);
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end generate GEN_IN;
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--First mixed column input
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out_array(0) <= in_array(0);
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out_array(1) <= in_array(5);
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out_array(2) <= in_array(10);
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out_array(3) <= in_array(15);
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-- Second mixed column input
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out_array(4) <= in_array(4);
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out_array(5) <= in_array(9);
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out_array(6) <= in_array(14);
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out_array(7) <= in_array(3);
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-- Third mixed column input
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out_array(8) <= in_array(8);
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out_array(9) <= in_array(13);
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out_array(10) <= in_array(2);
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out_array(11) <= in_array(7);
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-- Fourth mixed column input
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out_array(12) <= in_array(12);
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out_array(13) <= in_array(1);
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out_array(14) <= in_array(6);
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out_array(15) <= in_array(11);
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-- Output generation
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GEN_OUT: for i in 15 downto 0 generate
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data_out(i*8+7 downto i*8) <= out_array(15-i);
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end generate GEN_OUT;
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end architecture RTL; |