51 lines
1.6 KiB
VHDL
51 lines
1.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity mix_columns is
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port(
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data_in : in std_logic_vector(127 downto 0);
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data_out : out std_logic_vector(127 downto 0)
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);
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end entity mix_columns;
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architecture RTL of mix_columns is
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-- Internal signals
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type data_array is array (15 downto 0) of std_logic_vector(7 downto 0);
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-- x1, x2, x3 multiplication
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signal in_array, out_array, in_array_x2, in_array_x3 : data_array;
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begin
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-- Input generation
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GEN_IN: for i in 15 downto 0 generate
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in_array(15-i) <= data_in(i*8+7 downto i*8);
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end generate GEN_IN;
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-- Multiplication
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GEN_M: for i in 15 downto 0 generate
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-- x2
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in_array_x2(15-i) <=
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(in_array(15-i)(6 downto 0) & '0') xor "00011011" when in_array(15-i)(7) = '1' else
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(in_array(15-i)(6 downto 0) & '0');
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-- x3
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in_array_x3(15-i) <=
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(in_array(15-i)(6 downto 0) & '0') xor in_array(15-i) xor "00011011" when in_array(15-i)(7) = '1' else
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(in_array(15-i)(6 downto 0) & '0') xor in_array(15-i);
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end generate GEN_M;
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-- Mixed columns generation
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GEN_MC: for i in 0 to 3 generate
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out_array(4*i) <= in_array_x2(4*i) xor in_array_x3(4*i+1) xor in_array(4*i+2) xor in_array(4*i+3);
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out_array(4*i+1) <= in_array(4*i) xor in_array_x2(4*i+1) xor in_array_x3(4*i+2) xor in_array(4*i+3);
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out_array(4*i+2) <= in_array(4*i) xor in_array(4*i+1) xor in_array_x2(4*i+2) xor in_array_x3(4*i+3);
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out_array(4*i+3) <= in_array_x3(4*i) xor in_array(4*i+1) xor in_array(4*i+2) xor in_array_x2(4*i+3);
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end generate;
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-- Output generation
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GEN_O: for i in 15 downto 0 generate
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data_out(i*8+7 downto i*8) <= out_array(15-i);
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end generate GEN_O;
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end architecture RTL; |