66 lines
2.0 KiB
VHDL
66 lines
2.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.rounds.all;
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entity key_top is
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generic(
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NPAR : integer := 2;
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KEY_WIDTH : integer := 128;
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KEY_ROUNDS: integer := 11;
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OPERATION : integer := 0 -- [0-encryption, 1-decryption]
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);
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port(
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clk : in std_logic;
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reset_n : in std_logic;
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stall : in std_logic;
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-- Key
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key_in : in std_logic_vector(KEY_WIDTH-1 downto 0);
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keyVal_in : in std_logic;
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keyVal_out: out std_logic;
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key_out : out std_logic_vector(KEY_ROUNDS*KEY_WIDTH-1 downto 0)
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);
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end entity key_top;
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architecture RTL of key_top is
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type keep_array is array (NPAR-1 downto 0) of std_logic_vector(15 downto 0);
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--variable key_rounds : integer := key_rounds_number(KEY_WIDTH);
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-- Internal signals
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signal key_exp : std_logic_vector(key_rounds_number(KEY_WIDTH)*KEY_WIDTH-1 downto 0);
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signal key_op: std_logic_vector(key_rounds_number(KEY_WIDTH)*KEY_WIDTH-1 downto 0);
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begin
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-- Instantiate key pipeline
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GEN_KEY_PIPE: entity work.key_pipeline
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generic map(
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KEY_WIDTH => KEY_WIDTH,
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KEY_ROUNDS => key_rounds_number(KEY_WIDTH)
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)
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port map(
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clk => clk,
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reset_n => reset_n,
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keyVal_in => keyVal_in,
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keyVal_out => keyVal_out,
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key_in => key_in,
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key_out => key_exp
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);
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-- Gen key depending on the OPERATION
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GEN_KEY_ENC: if OPERATION=0 generate
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key_op <= key_exp;
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end generate GEN_KEY_ENC;
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GEN_KEY_DEC: if OPERATION=1 generate
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GEN_KEY: for i in 0 to encrypt_rounds_number(KEY_WIDTH)+1 generate --ENC_ROUNDS
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key_op(128*i+127 downto 128*i) <= key_exp((encrypt_rounds_number(KEY_WIDTH)+1-i)*128+127 downto (encrypt_rounds_number(KEY_WIDTH)+1-i)*128);
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end generate GEN_KEY;
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end generate GEN_KEY_DEC;
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key_out <= key_op;
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end architecture RTL; |