86 lines
2.7 KiB
VHDL
86 lines
2.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity data_pipeline is
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generic(
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NPAR : integer := 2;
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ENC_ROUNDS: integer := 10
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);
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port(
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clk : in std_logic;
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reset_n : in std_logic;
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stall : in std_logic;
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-- Control
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keep_in : in std_logic_vector(NPAR*16-1 downto 0);
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keep_out : out std_logic_vector(NPAR*16-1 downto 0);
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-- Data
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data_in : in std_logic_vector(NPAR*128-1 downto 0);
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data_out : out std_logic_vector(NPAR*128-1 downto 0)
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);
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end entity data_pipeline;
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architecture RTL of data_pipeline is
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-- Internal signals
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type dVal_array is array ((ENC_ROUNDS) downto 0) of std_logic;
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type data_array is array ((ENC_ROUNDS) downto 0) of std_logic_vector(NPAR*128-1 downto 0);
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type last_array is array ((ENC_ROUNDS) downto 0) of std_logic;
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type keep_array is array ((ENC_ROUNDS) downto 0) of std_logic_vector(NPAR*16-1 downto 0);
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signal dVal_pipe : dVal_array; -- Data valid signal pipeline
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signal data_pipe : data_array; -- Data pipeline
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signal last_pipe : last_array;
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signal keep_pipe : keep_array;
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begin
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-- Instantiate data stages
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GEN_DAT: for i in 0 to ENC_ROUNDS generate
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GEN_D0: if i = 0 generate
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D0: entity work.pipe_reg
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generic map(
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DATA_WIDTH => NPAR*128
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)
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port map(
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clk => clk,
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reset_n => reset_n,
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stall => stall,
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last_in => '0',
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last_out => last_pipe(0),
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keep_in => keep_in,
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keep_out => keep_pipe(0),
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dVal_in => '1',
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dVal_out => dVal_pipe(0),
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data_in => data_in,
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data_out => data_pipe(0)
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);
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end generate GEN_D0;
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GEN_DX: if i > 0 generate
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DX: entity work.pipe_reg
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generic map(
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DATA_WIDTH => NPAR*128
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)
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port map(
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clk => clk,
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reset_n => reset_n,
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stall => stall,
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last_in => last_pipe(i-1),
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last_out => last_pipe(i),
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keep_in => keep_pipe(i-1),
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keep_out => keep_pipe(i),
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dVal_in => dVal_pipe(i-1),
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dVal_out => dVal_pipe(i),
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data_in => data_pipe(i-1),
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data_out => data_pipe(i)
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);
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end generate GEN_DX;
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end generate GEN_DAT;
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keep_out <= keep_pipe(ENC_ROUNDS);
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data_out <= data_pipe(ENC_ROUNDS);
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end architecture RTL; |