64 lines
1.8 KiB
VHDL
64 lines
1.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity aes_round_last is
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generic(
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OPERATION : integer := 0 -- [0-encryption, 1-decryption]
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);
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port(
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key_in : in std_logic_vector(127 downto 0);
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key_last : in std_logic_vector(127 downto 0);
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data_in : in std_logic_vector(127 downto 0);
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data_out : out std_logic_vector(127 downto 0)
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);
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end entity aes_round_last;
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architecture RTL of aes_round_last is
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-- Internal signals
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signal data_step_one : std_logic_vector(127 downto 0);
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signal data_step_two : std_logic_vector(127 downto 0);
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begin
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-- Encryption
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GEN_ENC: if OPERATION = 0 generate
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-- S-box stage
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GEN_SBOX: for i in 0 to 15 generate
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SBOX: entity work.s_box_lut port map(
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data_in => data_in(8*i+7 downto 8*i),
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data_out => data_step_one(8*i+7 downto 8*i)
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);
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end generate GEN_SBOX;
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-- Shift row
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GEN_SROW: entity work.shift_rows port map(
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data_in => data_step_one,
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data_out => data_step_two
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);
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end generate GEN_ENC;
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-- Decryption
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GEN_DEC: if OPERATION = 1 generate
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-- Inverse Shift row
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GEN_INV_SROW: entity work.inv_shift_rows port map(
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data_in => data_in,
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data_out => data_step_one
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);
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-- Inverse S-box stage
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GEN_INV_SBOX: for i in 0 to 15 generate
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INV_SBOX: entity work.inv_s_box_lut port map(
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data_in => data_step_one(8*i+7 downto 8*i),
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data_out => data_step_two(8*i+7 downto 8*i)
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);
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end generate GEN_INV_SBOX;
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end generate GEN_DEC;
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-- Last add round key
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data_out <= data_step_two xor key_in;
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end architecture RTL; |