129 lines
4.4 KiB
VHDL
129 lines
4.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity aes_pipeline is
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generic(
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KEY_WIDTH : integer := 128;
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KEY_ROUNDS: integer := 11;
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ENC_ROUNDS: integer := 10;
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OPERATION : integer := 0; --[0-encryption, 1-decryption]
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MODE : integer := 0 --[0-ECB, 1-CTR, 2-CBC]
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);
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port(
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clk : in std_logic;
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reset_n : in std_logic;
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stall : in std_logic;
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-- Key
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key_in : in std_logic_vector(KEY_ROUNDS*KEY_WIDTH-1 downto 0);
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last_in : in std_logic;
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last_out : out std_logic;
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keep_in : in std_logic_vector(15 downto 0);
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keep_out : out std_logic_vector(15 downto 0);
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-- Data valid
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dVal_in : in std_logic; -- Data valid
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dVal_out : out std_logic;
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-- Data
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data_in : in std_logic_vector(127 downto 0);
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data_out : out std_logic_vector(127 downto 0);
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-- CTR
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cntr_in : in std_logic_vector(127 downto 0)
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);
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end entity aes_pipeline;
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architecture RTL of aes_pipeline is
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-- Internal signals
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type dVal_array is array ((ENC_ROUNDS) downto 0) of std_logic;
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type data_array is array ((ENC_ROUNDS) downto 0) of std_logic_vector(127 downto 0);
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type last_array is array ((ENC_ROUNDS) downto 0) of std_logic;
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type keep_array is array ((ENC_ROUNDS) downto 0) of std_logic_vector(15 downto 0);
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signal s_data_to_block : std_logic_vector(127 downto 0);
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signal s_data_from_block : std_logic_vector(127 downto 0);
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signal dVal_pipe : dVal_array; -- Data valid signal pipeline
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signal data_pipe : data_array; -- Data pipeline
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signal last_pipe : last_array;
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signal keep_pipe : keep_array;
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begin
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GEN_EBC: if (MODE = 0) generate
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s_data_to_block <= data_in;
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s_data_from_block <= data_pipe(ENC_ROUNDS);
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end generate GEN_EBC;
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GEN_CTR: if (MODE = 1) generate
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s_data_to_block <= data_in;
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s_data_from_block <= cntr_in xor data_pipe(ENC_ROUNDS);
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end generate GEN_CTR;
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GEN_CBC: if (MODE = 2) generate
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-- encryption
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GEN_CBC_EN: if (OPERATION = 0) generate
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s_data_to_block <= data_in xor cntr_in;
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s_data_from_block <= data_pipe(ENC_ROUNDS);
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end generate GEN_CBC_EN;
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-- decryption
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GEN_CBC_DE: if (OPERATION = 1) generate
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s_data_to_block <= data_in;
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s_data_from_block <= cntr_in xor data_pipe(ENC_ROUNDS);
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end generate GEN_CBC_DE;
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end generate GEN_CBC;
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-- Instantiate regular AES stages
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GEN_AES: for i in 0 to ENC_ROUNDS generate
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GEN_S0: if i = 0 generate
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S0: entity work.aes_pipe_stage
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generic map(
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OPERATION => OPERATION
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)
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port map(
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clk => clk,
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reset_n => reset_n,
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stall => stall,
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key_in => key_in(255 downto 128),
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last_in => last_in,
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last_out => last_pipe(0),
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keep_in => keep_in,
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keep_out => keep_pipe(0),
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dVal_in => dVal_in,
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dVal_out => dVal_pipe(0),
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data_in => (s_data_to_block xor key_in(127 downto 0)),
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data_out => data_pipe(0)
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);
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end generate GEN_S0;
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GEN_SX: if i > 0 generate
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SX: entity work.aes_pipe_stage
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generic map(
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OPERATION => OPERATION,
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LAST => (i=ENC_ROUNDS)
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)
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port map(
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clk => clk,
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reset_n => reset_n,
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stall => stall,
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key_in => key_in(128*(i+1)+127 downto 128*(i+1)),
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last_in => last_pipe(i-1),
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last_out => last_pipe(i),
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keep_in => keep_pipe(i-1),
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keep_out => keep_pipe(i),
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dVal_in => dVal_pipe(i-1),
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dVal_out => dVal_pipe(i),
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data_in => data_pipe(i-1),
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data_out => data_pipe(i)
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);
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end generate GEN_SX;
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end generate GEN_AES;
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last_out <= last_pipe(ENC_ROUNDS);
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keep_out <= keep_pipe(ENC_ROUNDS);
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dVal_out <= dVal_pipe(ENC_ROUNDS);
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data_out <= s_data_from_block;
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end architecture RTL; |